Low Latency 100G Ethernet Intel® FPGA IP Core User Guide: For Intel® Stratix® 10 Devices

ID 683100
Date 2/16/2022
Document Table of Contents

6.6. Miscellaneous Status and Debug Signals

The miscellaneous status and debug signals are asynchronous.
Table 17.  Miscellaneous Status and Debug Signals




tx_lanes_stable Output Asserted when all four physical TX lanes are stable and ready to transmit data.
rx_block_lock Output Asserted when all 20 virtual lanes have identified 66-bit block boundaries in the serial data stream.
rx_am_lock Output Asserted when all 20 incoming virtual lanes have been ordered.
rx_pcs_ready Output Asserted when the RX lanes are fully aligned and ready to receive data.