Low Latency 100G Ethernet Intel® FPGA IP Core User Guide: For Intel® Stratix® 10 Devices

ID 683100
Date 2/16/2022
Public
Document Table of Contents

7.8.27. Link Training Config Register for Lane 2

Link Training Config Register for Lane 2 Provides CSRs for the following link training features
  • LT PRBS Pattern Select for lane 2
  • LT PRBS Seed for lane 2

Offset: 0xE4

Access: RW

Link Training Config Register for Lane 2 Fields

Bit Name Description Access Reset
26:16 lt_prbs_seed_ln2 Link Training PRBS Seed for Lane 2

Sets the initial seed for PRBS. Default value is 11'h72d

RW 0x72D
2:0 lt_prbs_pattern_select_ln2 Link Training PRBS Pattern Select for Lane 2

0: Use Clause 92 Polynomial 0

1: Use Clause 92 Polynomial 1

2: Use Clause 92 Polynomial 2

3: Use Clause 92 Polynomial 3

4: Use Clause 72 Polynomial (if CL72 PRBS parameter is enabled)

All other settings reserved

  • Default value for lane 2 is 2
RW 0x2

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