Low Latency 100G Ethernet Intel® FPGA IP Core User Guide: For Intel® Stratix® 10 Devices

ID 683100
Date 2/16/2022
Document Table of Contents
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4.3.4. Low Latency 100G Ethernet Intel FPGA IP Core CRC Checking

The 32-bit CRC field is received in the order: X32, X30, . . . X1, and X0 , where X32 is the most significant bit of the FCS field and occupies the least significant bit position in the first FCS byte.

If the RX MAC detects a CRC32 error, it marks the frame invalid by asserting l8_rx_error[1].