Low Latency 100G Ethernet Intel® FPGA IP Core User Guide: For Intel® Stratix® 10 Devices

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ID 683100
Date 2/16/2022
Public
Document Table of Contents

1. Low Latency 100G Ethernet Intel FPGA IP Overview

Updated for:
Intel® Quartus® Prime Design Suite 21.1
IP Version 19.2.0

The Low Latency 100G Ethernet Intel FPGA IP core offers low round-trip latency and small size to implement the IEEE 802.3ba and 802.3bj High Speed Ethernet Standard .

The Low Latency 100G Ethernet Intel FPGA IP is used in multiple variants of the Intel® Stratix® 10 device family. Refer to the Ethernet IP Naming Convention table to view the device-specific IP name.

The device-specific IP naming convention of Intel Stratix 10 displayed in IP catalog is Low Latency 100G Ethernet Intel FPGA. The IP core is included in the Intel FPGA IP Library and is available from the Intel Quartus® Prime Pro Edition IP Catalog.

Attention: In this document, unless specified, the Low Latency 100G Ethernet Intel FPGA IP refers to all supported device families.
Figure 1.  Low Latency 100G Ethernet Intel FPGA IP CoreMain blocks, internal connections, and external block requirements.

The MAC client-side Avalon® streaming interface (Avalon-ST) data bus is 512 bits wide. The client-side data maps to four 25.78125 Gbps transceiver PHY links.

The FPGA serial transceivers are compliant with the IEEE 802.3ba standard CAUI-4 specification. You can connect the transceiver interfaces directly to an external physical medium dependent (PMD) optical module or to another device.

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