Low Latency 100G Ethernet Intel® FPGA IP Core User Guide: For Intel® Stratix® 10 Devices

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ID 683100
Date 2/16/2022
Public
Document Table of Contents

7.8.13. Auto Negotiation Status Register 4

This register provides the upper bits of the AN RX Next page received from the link partner.

Offset: 0xCA

Access: RO

Auto Negotiation Status Register 4 Fields

Bit Name Description Access Reset
31:0 lp_next_page_high Link Partner Next Page (upper bits)

[31:0]: Link partner Unformatted bits

[47:16] or [31:0]

RO 0x0

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