Low Latency 100G Ethernet Intel® FPGA IP Core User Guide: For Intel® Stratix® 10 Devices

ID 683100
Date 2/16/2022
Document Table of Contents

7.8.8. Auto Negotiation Config Register 5

Provides the following configuration options
  • User next page (lower bits)
  • Override AN_TECH []

Offset: 0xC5

Access: RW

Auto Negotiation Config Register 5 Fields

Bit Name Description Access Reset
31:16 override_an_tech_22_8 AN_TECH Override Value, bits [22:8]

When Override AN Parameters is enabled (override_an_parameters_enable=1), this register controls the upper bits of AN_TECH used in the AN Base page

[0]: 100GBASE-CR4

All other settings Reserved

RW 0x0
15:0 user_next_page_low User Controlled AN Next page (lower bits)

When User Controlled next gates are turned on (an_next_pages_ctrl=1), this register provides the lower bits of the User Next page that is used instead of the default page

[15]: Next page bit

[14]: ACK bit (controlled by the TX SM)

[13]: MP bit (Message vs. Unformatted)

[12]: ACK2 bits

[11]: Toggle bit (controlled by the TX SM)

[10:0]: Message code field [10:0]/Unformatted code field[10:0]

RW 0x0

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