Low Latency 100G Ethernet Intel® FPGA IP Core User Guide: For Intel® Stratix® 10 Devices

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ID 683100
Date 2/16/2022
Public
Document Table of Contents

7.8.29. Local Transceiver TX EQ 1 Settings for Lane 2

Provides the following Local TX EQ 1 Settings for Lane 2
  • Local TX EQ VOD Setting for Lane 2
  • Local TX EQ Post-Tap Setting for Lane 2
  • Local TX EQ Pre-Tap Setting for Lane 2

Offset: 0xE6

Access: RO

Local Transceiver TX EQ 1 Settings for Lane 2 Fields

Bit Name Description Access Reset
20:16 lt_pretap_setting_ln2 Local TX EQ Pre-tap Setting for Lane 2

This register returns the most recent Pre-tap setting that was written to the local transceiver.

RO 0x0
13:8 lt_posttap_setting_ln2 Local TX EQ Post-tap Setting for Lane 2

This register returns the most recent Post-tap setting that was written to the local transceiver

RO 0x0
4:0 lt_vod_setting_ln2 Local TX EQ VOD Setting for Lane 2

This register returns the most recent VOD setting that was written to the local transceiver

RO 0x0

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