Low Latency 100G Ethernet Intel® FPGA IP Core User Guide: For Intel® Stratix® 10 Devices

ID 683100
Date 2/16/2022
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4.3.2. IP Core Strict SFD Checking

The Low Latency 100G Ethernet Intel FPGA IP core RX MAC checks all incoming packets for a correct Start byte (0xFB). If you turn on Enable Strict SFD check in the Low Latency 100G Ethernet Intel FPGA parameter editor, you enable the RX MAC to check the incoming preamble and SFD for the following values:

  • SFD = 0xD5
  • Preamble = 0x555555555555

The RX MAC checks one or both of these values depending on the values in bits [4:3] of the RXMAC_CONTROL register at offset 0x50A.

Table 10.  Strict SFD Checking Configuration
Enable Strict SFD check 0x50A[4]: Preamble Check 0x50A[3]: SFD Check Fields Checked Behavior if Check Fails
Off Don't Care Don't Care Start byte IP core does not recognize a malformed Start byte as a Start byte
On 0 0 Start byte
0 1 Start byte and SFD IP Core drops the packet
1 0 Start byte and preamble
1 1 Start byte and preamble and SFD