Low Latency 100G Ethernet Intel® FPGA IP Core User Guide: For Intel® Stratix® 10 Devices

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ID 683100
Date 2/16/2022
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Document Table of Contents
Document Table of Contents x
1. Low Latency 100G Ethernet Intel FPGA IP Overview 2. Getting Started 3. IP Core Parameters 4. Functional Description 5. Reset 6. Interfaces and Signal Descriptions 7. Registers 8. Debugging the Link 9. Ethernet Toolkit Overview 10. Low Latency 100G Ethernet Intel FPGA IP Core User Guide Archives 11. Document Revision History for the Low Latency 100G Ethernet Intel FPGA IP Core User Guide
1. Low Latency 100G Ethernet Intel FPGA IP Overview x
1.1. Low Latency 100G Ethernet Intel FPGA IP Core Supported Features 1.2. IP Core Device Family and Speed Grade Support 1.3. IP Core Verification 1.4. Performance and Resource Utilization 1.5. Release Information
1.2. IP Core Device Family and Speed Grade Support x
1.2.1. Low Latency 100G Ethernet Intel FPGA IP Core Device Family Support 1.2.2. Low Latency 100G Ethernet Intel FPGA IP Core Device Speed Grade Support
1.3. IP Core Verification x
1.3.1. Simulation Environment 1.3.2. Compilation Checking 1.3.3. Hardware Testing
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying the IP Core Parameters and Options 2.3. Simulating the IP Core 2.4. Generated File Structure 2.5. Integrating Your IP Core in Your Design 2.6. IP Core Testbenches 2.7. Compiling the Full Design and Programming the FPGA
2.5. Integrating Your IP Core in Your Design x
2.5.1. Pin Assignments 2.5.2. Adding the Transceiver PLLs 2.5.3. Placement Settings for the Low Latency 100G Ethernet Intel FPGA IP Core
4. Functional Description x
4.1. High Level System Overview 4.2. Low Latency 100G Ethernet Intel FPGA IP Core TX Datapath 4.3. Low Latency 100G Ethernet Intel FPGA IP Core RX Datapath 4.4. Flow Control 4.5. User Interface to Ethernet Transmission 4.6. Auto Negotiation and Link Training 4.7. Auto Adaptation
4.2. Low Latency 100G Ethernet Intel FPGA IP Core TX Datapath x
4.2.1. Preamble, Start, and SFD Insertion 4.2.2. Length/Type Field Processing 4.2.3. Frame Padding 4.2.4. Frame Check Sequence (CRC-32) Insertion 4.2.5. Inter-Packet Gap Adjustment 4.2.6. Error Insertion Test and Debug Feature 4.2.7. TX PCS 4.2.8. TX RSFEC
4.3. Low Latency 100G Ethernet Intel FPGA IP Core RX Datapath x
4.3.1. Low Latency 100G Ethernet Intel FPGA IP Core Preamble Processing 4.3.2. IP Core Strict SFD Checking 4.3.3. Low Latency 100G Ethernet Intel FPGA IP Core FCS (CRC-32) Removal 4.3.4. Low Latency 100G Ethernet Intel FPGA IP Core CRC Checking 4.3.5. Low Latency 100G Ethernet Intel FPGA IP Core Malformed Packet Handling 4.3.6. RX CRC Forwarding 4.3.7. Inter-Packet Gap 4.3.8. RX PCS 4.3.9. RX RSFEC
4.4. Flow Control x
4.4.1. TX Pause/PFC Flow Control Transmission 4.4.2. XON/XOFF Pause Frames
4.5. User Interface to Ethernet Transmission x
4.5.1. Order of Transmission 4.5.2. Bit Order For TX and RX Datapaths
6. Interfaces and Signal Descriptions x
6.1. TX MAC Interface to User Logic 6.2. RX MAC Interface to User Logic 6.3. Transceivers 6.4. Transceiver Reconfiguration Signals 6.5. Avalon-MM Management Interface 6.6. Miscellaneous Status and Debug Signals 6.7. Reset Signals 6.8. Clocks 6.9. Flow Control Interface
6.4. Transceiver Reconfiguration Signals x
6.4.1. Disabling Background Calibration
7. Registers x
7.1. PHY Registers 7.2. TX MAC Registers 7.3. RX MAC Registers 7.4. Pause/PFC Flow Control Registers 7.5. Statistics Registers 7.6. TX Reed-Solomon FEC Registers 7.7. RX Reed-Solomon FEC Registers 7.8. Auto-Negotiation and Link Training Registers
7.5. Statistics Registers x
7.5.1. TX Statistics Registers 7.5.2. RX Statistics Registers
7.8. Auto-Negotiation and Link Training Registers x
7.8.1. AN/LT Sequencer Config 7.8.2. AN/LT Sequencer Status 7.8.3. Auto Negotiation Config Register 1 7.8.4. Auto Negotiation Config Register 2 7.8.5. Auto Negotiation Status Register 7.8.6. Auto Negotiation Config Register 3 7.8.7. Auto Negotiation Config Register 4 7.8.8. Auto Negotiation Config Register 5 7.8.9. Auto Negotiation Config Register 6 7.8.10. Auto Negotiation Status Register 1 7.8.11. Auto Negotiation Status Register 2 7.8.12. Auto Negotiation Status Register 3 7.8.13. Auto Negotiation Status Register 4 7.8.14. Auto Negotiation Status Register 5 7.8.15. Link Training Config Register 1 7.8.16. Link Training Config Register 2 7.8.17. Link Training Status Register 1 7.8.18. Link Training Config Register for Lane 0 7.8.19. Link Training Frame Contents for Lane 0 7.8.20. Local Transceiver TX EQ 1 Settings for Lane 0 7.8.21. Local Transceiver TX EQ 2 Settings for Lane 0 7.8.22. Local Link Training Parameters 7.8.23. Link Training Config Register for Lane 1 7.8.24. Link Training Frame Contents for Lane 1 7.8.25. Local Transceiver TX EQ 1 Settings for Lane 1 7.8.26. Local Transceiver TX EQ 2 Settings for Lane 1 7.8.27. Link Training Config Register for Lane 2 7.8.28. Link Training Frame Contents for Lane 2 7.8.29. Local Transceiver TX EQ 1 Settings for Lane 2 7.8.30. Local Transceiver TX EQ 2 Settings for Lane 2 7.8.31. Link Training Config Register for Lane 3 7.8.32. Link Training Frame Contents for Lane 3 7.8.33. Local Transceiver TX EQ 1 Settings for Lane 3 7.8.34. Local Transceiver TX EQ 2 Settings for Lane 3
9. Ethernet Toolkit Overview x
9.1. Features
1. Low Latency 100G Ethernet Intel FPGA IP Overview
2. Getting Started
3. IP Core Parameters
4. Functional Description
5. Reset
6. Interfaces and Signal Descriptions
7. Registers
8. Debugging the Link
9. Ethernet Toolkit Overview
10. Low Latency 100G Ethernet Intel FPGA IP Core User Guide Archives
11. Document Revision History for the Low Latency 100G Ethernet Intel FPGA IP Core User Guide

7.4. Pause/PFC Flow Control Registers

Some of the registers in this table cannot be updated during normal operation. To ensure correct operation, perform a soft reset by writing Bit[0] of the PHY_CONFIG (0x310) after updating registers that cannot be changed dynamically.
Table 26.  TX Flow Control Registers
Addr Bit Name Description Reset Access
0x600 31:0 TX Flow Control Revision ID

Specifies the revision ID, "100GFCTx CSR"

0x0809_20017

 RO
0x601 31:0 TX Flow Control Scratch Pad Scratch register for testing. 0 RW
0x602 31:0 TX Flow Control IP Core Variant 0

Specifies first 4 characters of IP core variation identifier ASCII string, "100G".

0x3130_3047

 RO
0x603 31:0 TX Flow Control IP Core Variant 1 Next 4 characters of IP core variation identifier ASCII string, "FCTx" 0x4643_5478 RO
0x604 31:0 TX Flow Control IP Core Variant 2

Final 4 characters of IP core variation identifier ASCII string, "xCSR".

0x0043_5352 RO
0x605

7:0

TX Flow Control Enable

One bit per queue

 Enables the IP core to generate XON and XOFF Pause/PFC flow control frames to the remote partner. The following encodings are defined:
  • 1'b0: XON or XOFF Pause/PFC flow control is disabled
  • 1'b1: XON or XOFF Pause/PFC flow control is enabled.

You can change this field dynamically.

0xFF

 RW

31:8

 Reserved Reserved 0 RO
0x606

7:0

TX Flow Control CSR XON/XOFF Request 0

XON/XOF flow control frame request bit 0. Interpretation depends on whether the IP core is in 1-bit FC request mode or in 2-bit FC request mode. This register affects a flow control queue only if the corresponding bit of the TX Flow Control Enable register has the value of 1.

In 2-bit mode, in addition, this register is active for a specific flow control queue only if the corresponding bit in the TX 2-bit Flow Control Request Mode register field (bits 7:0 of the register at offset 0x641) specifies that the flow control logic accepts input from this register.

The following encodings are defined for 1-bit mode. The IP core reads the 1-bit mode value in TX Flow Control CSR XON/XOFF Request 0.

  • 0 = No request
  • 0 to 1 = Generate XOFF request
  • 1 = Continue to generate XOFF request
  • 1 to 0 = Generate XON request

The following encodings are defined for 2-bit mode. The IP core reads the 2-bit mode value in {TX Flow Control CSR XON/XOFF Request 1, TX Flow Control CSR XON/XOFF Request 1}.

  • 00 = No request
  • 01 = XON request
  • 10 = XOFF request
  • 11 = Invalid

You can modify the value of this field dynamically.

0 RW

15:8

 Reserved Reserved 0 RO

23:16

TX Flow Control CSR XON/XOFF Request 1

In conjunction with Flow Control XON/XOFF Request 0 specifies a 2-bit request for XON/XOFF flow control frame transmission. This bit is the upper bit of the 2-bit control field.

You can change the value of this field dynamically.

0 RW

31:24

 Reserved Reserved 0 RO
0x60A 0

TX Pause Enable

1-bit

Determines whether receiving a valid Pause frame stops TX user data transmission.

1'b0: Transmission is not stopped

1b1: Transmission stops

You cannot change the value of this field dynamically.

0 RW
31:1 Reserved Reserved 0 RO
0x60D 31:0 TX Flow Control Destination Address Lower

Specifies the 48-bit Destination Address of the flow control frame. Contains the 32 LSB of the address field.

You cannot modify the value of this field dynamically.

0xC2000001 RW
0x60E 15:0 TX Flow Control Destination Address Upper

Specifies the 48-bit Destination Address of flow control frame. Contains the 16 MSB of the address field.

You cannot modify the value of this field dynamically.

0x0180 RW
31:16 Reserved Reserved 0 RO
0x60F 31:0 TX Flow Control Source Address Lower

Specifies the 48-bit Source Address of flow control frame. Contains the 32 LSB of the address field.

0xCBFC5ADD RW
0x610 15:0 TX Flow Control Source Address Upper

Specifies the 48-bit Source Address of flow control frame. Contains the 16 MSB of the address field.

You cannot modify the value of this field dynamically.

0xE100 RW
31:16 Reserved Reserved 0 RO

0x620, 0x621, …, 0x620+(FCQN-1 where FCQN = 0 to 7)

15:0

TX Flow Control Quanta

16-bit per FCQN

Specifies the pause quanta of Pause/PFC flow control frames to be sent to remote partner.

You cannot modify the value of this field dynamically.

0xFFFF RW
31:16 Reserved Reserved 0 RO
0x628, 0x629, …, 0x628+(FCQN-1 where FCQN = 0 to 7) 15:0

TX Flow Control Signal XOFF Request Hold Quanta

16-bit per FCQN

Specifies the separation between 2 consecutive XOFF flow control frames.

You cannot modify the value of this field dynamically.

0xFFFF RW
31:16 Reserved Reserved 0 RO
0x640 0

TX Flow Control Select

1-bit

Specifies whether the TX hardware generates Pause or PFC frames. Affects only PFC Queue 0.

Usage example:

You can synthesize a single PFC queue and use it for both Pause and PFC purpose.

1'b0: Pause

1'b1: PFC

You cannot modify the value of this field dynamically.

1 RW
31:1 Reserved. Reserved. 0 RO
0x641 (FCQN-1):0

TX 2-bit Flow Control Request Mode

1-bit per FCQN

Determines whether the TX Flow Control CSR XON/XOFF Request register or the pause_insert_tx0 and pause_insert_tx1 signals control XON/XOFF mode in 2-bit control mode.

1'b0: The pause_insert_tx0 and pause_insert_tx1 signals control requests

1'b1: The TX Flow Control CSR XON/XOFF Request register fields control requests

You cannot modify the value of this field dynamically.

0 RW
16

TX Flow Control Request Mode

FCQN

Determines whether the IP core is in TX flow control 1-bit mode or 2-bit mode.

1'b0: Use 1-bit mode to make TX flow control requests

1'b1: Use 2-bit mode to make TX flow control requests

0 RW
31:17 Reserved Reserved 0 RO
Table 27.  RX Flow Control Registers
Addr Bit Name Description Reset Access
0x700 31:0 RX Flow Control Revision ID

Specifies the revision ID, "100GFCTx CSR"

0x0809_20017

 RO
0x701 31:0 RX Flow Control Scratch Pad Provides a register for debug. 0 RW
0x702 31:0 RX Flow Control IP Core Variant 0

First 4 characters of IP core variation identifier ASCII string,

Specifies first 4 characters of IP core variation identifier ASCII string, "100G".

0x3130_3047

 RO
0x703 31:0 RX Flow Control IP Core Variant 1 Next 4 characters of IP core variation identifier ASCII string, "FCRx". 0x4643_5278 RO
0x704 31:0 RX Flow Control IP Core Variant 2 Final 4 characters of IP core variation identifier ASCII string, "0CSR". The "0" is unprintable. 0x0043_5352 RO
0x705 7:0

RX PFC Enable

1 bit per queue

Determines whether receiving a valid PFC frame causes the PFC duration user interface to indicate a valid pause quanta duration to the user logic.

1'b0: Disable

1'b1: Enable

If flow control is disabled, RX MAC forwards any flow control packet to the user without generating XON, XOFF, or Pause indicators.

0xFF RW
31:8 Reserved Reserved 0 RO
0x707 31:0 RX Flow Control Destination Address Lower

Specifies the 48-bit Destination Address of the flow control frame. Contains the 32 LSB of the address field.

The flow control frame is sent with the destination address matching the address specified in this register or the multicast address. If the address is not a match, the Flow Control block does not respond to the incoming frame; the IP core just passes it through.

You cannot modify the value of this field dynamically.

0xC2000001 RW
0x708 15:0 RX Flow Control Destination Address Upper

Specifies the 48-bit Destination Address of flow control frame. Contains the 16 MSB of the address field.

The flow control frame is sent with the destination address matching the address specified in this register or the multicast address. If the address is not a match, the Flow Control block does not respond to the incoming frame; the IP core just passes it through.

You cannot modify the value of this field dynamically.

0x0180 RW
31:16 Reserved Reserved 0 RO
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