Low Latency 100G Ethernet Intel® FPGA IP Core User Guide: For Intel® Stratix® 10 Devices

ID 683100
Date 2/16/2022
Public
Document Table of Contents

6.4. Transceiver Reconfiguration Signals

You access the transceiver control and status registers using the transceiver reconfiguration interface. This is an Avalon® memory-mapped interface.

The Avalon® memory-mapped interface implements a standard memory-mapped protocol. You can connect an Avalon® master to this bus to access the registers of the embedded Native Transceiver PHY IP core.

Table 15.  Reconfiguration Interface Ports with Shared Native PHY Reconfiguration InterfaceAll interface signals are clocked by the reconfig_clk clock. These signals are provided by a four-channel Intel Stratix 10 Native PHY IP core embedded in the Low Latency 100G Ethernet Intel FPGA IP core.
Port Name Direction Description
reconfig_clk Input Avalon® clock. The clock frequency is 100-162 MHz. All transceiver reconfiguration interface signals are synchronous to reconfig_clk.
reconfig_reset Input Resets the Avalon® memory-mapped interface and all of the registers to which it provides access.
reconfig_write Input Write request signal. Signal is active high.
reconfig_read Input Read request signal. Signal is active high.
reconfig_address[12:0] Input Address bus. Refer to the L- and H-Tile Transceiver PHY User Guide for information about the address fields for the Native PHY four-channel configuration.
reconfig_writedata[31:0] Input A 32-bit data write bus. reconfig_address specifies the address.
reconfig_readdata[31:0] Output A 32-bit data read bus. Drives read data from the specified address. Signal is valid after reconfig_waitrequest is deasserted.
reconfig_waitrequest Output Indicates the Avalon® memory-mapped interface is busy. Keep the reconfig_write or reconfig_read asserted until reconfig_waitrequest is deasserted.

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