4.3.3. Low Latency 100G Ethernet Intel FPGA IP Core FCS (CRC-32) Removal
Independent user configuration register bits control FCS CRC removal at runtime. Bit 0 of the MAC_CRC_CONFIG register enables and disables CRC removal; by default, CRC removal is enabled.
In the user interface, the EOP signal (l8_rx_endofpacket) indicates the end of CRC bytes if CRC is not removed. When CRC is removed, the EOP signal indicates the final byte of payload.