Low Latency 100G Ethernet Intel® FPGA IP Core User Guide: For Intel® Stratix® 10 Devices

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ID 683100
Date 2/16/2022
Public
Document Table of Contents
Document Table of Contents x
1. Low Latency 100G Ethernet Intel FPGA IP Overview 2. Getting Started 3. IP Core Parameters 4. Functional Description 5. Reset 6. Interfaces and Signal Descriptions 7. Registers 8. Debugging the Link 9. Ethernet Toolkit Overview 10. Low Latency 100G Ethernet Intel FPGA IP Core User Guide Archives 11. Document Revision History for the Low Latency 100G Ethernet Intel FPGA IP Core User Guide
1. Low Latency 100G Ethernet Intel FPGA IP Overview x
1.1. Low Latency 100G Ethernet Intel FPGA IP Core Supported Features 1.2. IP Core Device Family and Speed Grade Support 1.3. IP Core Verification 1.4. Performance and Resource Utilization 1.5. Release Information
1.2. IP Core Device Family and Speed Grade Support x
1.2.1. Low Latency 100G Ethernet Intel FPGA IP Core Device Family Support 1.2.2. Low Latency 100G Ethernet Intel FPGA IP Core Device Speed Grade Support
1.3. IP Core Verification x
1.3.1. Simulation Environment 1.3.2. Compilation Checking 1.3.3. Hardware Testing
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying the IP Core Parameters and Options 2.3. Simulating the IP Core 2.4. Generated File Structure 2.5. Integrating Your IP Core in Your Design 2.6. IP Core Testbenches 2.7. Compiling the Full Design and Programming the FPGA
2.5. Integrating Your IP Core in Your Design x
2.5.1. Pin Assignments 2.5.2. Adding the Transceiver PLLs 2.5.3. Placement Settings for the Low Latency 100G Ethernet Intel FPGA IP Core
4. Functional Description x
4.1. High Level System Overview 4.2. Low Latency 100G Ethernet Intel FPGA IP Core TX Datapath 4.3. Low Latency 100G Ethernet Intel FPGA IP Core RX Datapath 4.4. Flow Control 4.5. User Interface to Ethernet Transmission 4.6. Auto Negotiation and Link Training 4.7. Auto Adaptation
4.2. Low Latency 100G Ethernet Intel FPGA IP Core TX Datapath x
4.2.1. Preamble, Start, and SFD Insertion 4.2.2. Length/Type Field Processing 4.2.3. Frame Padding 4.2.4. Frame Check Sequence (CRC-32) Insertion 4.2.5. Inter-Packet Gap Adjustment 4.2.6. Error Insertion Test and Debug Feature 4.2.7. TX PCS 4.2.8. TX RSFEC
4.3. Low Latency 100G Ethernet Intel FPGA IP Core RX Datapath x
4.3.1. Low Latency 100G Ethernet Intel FPGA IP Core Preamble Processing 4.3.2. IP Core Strict SFD Checking 4.3.3. Low Latency 100G Ethernet Intel FPGA IP Core FCS (CRC-32) Removal 4.3.4. Low Latency 100G Ethernet Intel FPGA IP Core CRC Checking 4.3.5. Low Latency 100G Ethernet Intel FPGA IP Core Malformed Packet Handling 4.3.6. RX CRC Forwarding 4.3.7. Inter-Packet Gap 4.3.8. RX PCS 4.3.9. RX RSFEC
4.4. Flow Control x
4.4.1. TX Pause/PFC Flow Control Transmission 4.4.2. XON/XOFF Pause Frames
4.5. User Interface to Ethernet Transmission x
4.5.1. Order of Transmission 4.5.2. Bit Order For TX and RX Datapaths
6. Interfaces and Signal Descriptions x
6.1. TX MAC Interface to User Logic 6.2. RX MAC Interface to User Logic 6.3. Transceivers 6.4. Transceiver Reconfiguration Signals 6.5. Avalon-MM Management Interface 6.6. Miscellaneous Status and Debug Signals 6.7. Reset Signals 6.8. Clocks 6.9. Flow Control Interface
6.4. Transceiver Reconfiguration Signals x
6.4.1. Disabling Background Calibration
7. Registers x
7.1. PHY Registers 7.2. TX MAC Registers 7.3. RX MAC Registers 7.4. Pause/PFC Flow Control Registers 7.5. Statistics Registers 7.6. TX Reed-Solomon FEC Registers 7.7. RX Reed-Solomon FEC Registers 7.8. Auto-Negotiation and Link Training Registers
7.5. Statistics Registers x
7.5.1. TX Statistics Registers 7.5.2. RX Statistics Registers
7.8. Auto-Negotiation and Link Training Registers x
7.8.1. AN/LT Sequencer Config 7.8.2. AN/LT Sequencer Status 7.8.3. Auto Negotiation Config Register 1 7.8.4. Auto Negotiation Config Register 2 7.8.5. Auto Negotiation Status Register 7.8.6. Auto Negotiation Config Register 3 7.8.7. Auto Negotiation Config Register 4 7.8.8. Auto Negotiation Config Register 5 7.8.9. Auto Negotiation Config Register 6 7.8.10. Auto Negotiation Status Register 1 7.8.11. Auto Negotiation Status Register 2 7.8.12. Auto Negotiation Status Register 3 7.8.13. Auto Negotiation Status Register 4 7.8.14. Auto Negotiation Status Register 5 7.8.15. Link Training Config Register 1 7.8.16. Link Training Config Register 2 7.8.17. Link Training Status Register 1 7.8.18. Link Training Config Register for Lane 0 7.8.19. Link Training Frame Contents for Lane 0 7.8.20. Local Transceiver TX EQ 1 Settings for Lane 0 7.8.21. Local Transceiver TX EQ 2 Settings for Lane 0 7.8.22. Local Link Training Parameters 7.8.23. Link Training Config Register for Lane 1 7.8.24. Link Training Frame Contents for Lane 1 7.8.25. Local Transceiver TX EQ 1 Settings for Lane 1 7.8.26. Local Transceiver TX EQ 2 Settings for Lane 1 7.8.27. Link Training Config Register for Lane 2 7.8.28. Link Training Frame Contents for Lane 2 7.8.29. Local Transceiver TX EQ 1 Settings for Lane 2 7.8.30. Local Transceiver TX EQ 2 Settings for Lane 2 7.8.31. Link Training Config Register for Lane 3 7.8.32. Link Training Frame Contents for Lane 3 7.8.33. Local Transceiver TX EQ 1 Settings for Lane 3 7.8.34. Local Transceiver TX EQ 2 Settings for Lane 3
9. Ethernet Toolkit Overview x
9.1. Features
1. Low Latency 100G Ethernet Intel FPGA IP Overview
2. Getting Started
3. IP Core Parameters
4. Functional Description
5. Reset
6. Interfaces and Signal Descriptions
7. Registers
8. Debugging the Link
9. Ethernet Toolkit Overview
10. Low Latency 100G Ethernet Intel FPGA IP Core User Guide Archives
11. Document Revision History for the Low Latency 100G Ethernet Intel FPGA IP Core User Guide

3. IP Core Parameters

The Low Latency 100G Ethernet Intel FPGA IP parameter editor provides the parameters you can set to configure the Low Latency 100G Ethernet Intel FPGA IP core and simulation and hardware design examples.

Low Latency 100G Ethernet Intel FPGA IP parameter editor includes an Example Design tab. For information about that tab, refer to the Design Example User Guide.

Table 9.   Low Latency 100G Ethernet Intel FPGA IP Parameters: Main TabDescribes the parameters for customizing the Low Latency 100G Ethernet Intel FPGA IP core on the Main tab of the Low Latency 100G Ethernet Intel FPGA IP parameter editor.

Parameter

Type

Range

Default Setting

Parameter Description

General Options
Device family

String

  • Stratix 10
 Default is set according to your Quartus project target device.

Selects the device family.

Target transceiver tile String
  • H-Tile
  • L-Tile
 Default is set according to your Quartus project target device. Selects the Intel® Stratix® 10 target transceiver tile. The value is set automatically according to your Quartus project target device.

PCS/PMA Options

Enable RS-FEC

Boolean

  • True
  • False
 False If this parameter is turned on, the IP core implements Reed-Solomon forward error correction (FEC) RS-FEC(528, 514).

PHY reference frequency

Integer (encoding)

  • 644.53125 MHz
  • 322.265625 MHz

644.53125 MHz

Sets the expected incoming PHY clk_ref reference frequency. The input clock frequency must match the frequency you specify for this parameter (± 100ppm).

Flow Control Options

Enable MAC Flow Control

Boolean

  • True
  • False
False

If turned on, the IP core enables the flow control mechanism and generates the pause_insert_tx [1:0] and pause_receive_rx signals. If turned off, the IP core disables the flow control mechanism.

Number of queues in priority flow control Integer

1–8

1

Number of distinct priority queues for priority-based flow control.

MAC Options

Enable link fault generation

Boolean

  • True
  • False

False

If turned on, the IP core includes the link fault signaling modules and relevant signals. If turned off, the IP core is configured without these modules and without these signals. Turning on link fault signaling provides your design a tool to improve reliability, but increases resource utilization.

Enable TX CRC insertion

Boolean

  • True
  • False

True

If turned on, the IP core inserts a 32-bit Frame Check Sequence (FCS), which is a CRC-32 checksum, in outgoing Ethernet frames. If turned off, the IP core does not insert the CRC-32 sequence in outgoing Ethernet communication. Turning on TX CRC insertion improves reliability but increases resource utilization and latency through the IP core.

If you turn on flow control, the IP core must be configured with TX CRC insertion, and this parameter is not available.

Enable preamble passthrough

Boolean

  • True
  • False

False

If turned on, the IP core is in RX and TX preamble pass-through mode. In RX preamble pass-through mode, the IP core passes the preamble and SFD to the client instead of stripping them out of the Ethernet packet. In TX preamble pass-through mode, the client specifies the preamble to be sent in the Ethernet frame.

Enable RX/TX statistics counters Boolean
  • True
  • False
 True If turned on, the IP core includes built–in TX and RX statistics counters. If turned off, the IP core is configured without statistics counters. In any case, the IP core outputs frame status flags for the current input or output data.
Enable Strict SFD check Boolean
  • True
  • False
False If turned on, the IP core can implement strict SFD checking, depending on register settings.

Configuration, Debug and Extension Options

Enable Native PHY Debug Master Endpoint (NPDME)

Boolean

  • True
  • False

False

If turned on, the IP core turns on the following features in the Native PHY IP core that is included in the Low Latency 100G Ethernet Intel FPGA IP core:

  • Enable Native PHY Debug Master Endpoint (NPDME)
  • Enable capability registers

If turned off, the IP core is configured without these features.

Enable JTAG to Avalon Master Bridge

Boolean

  • True
  • False

False

If turned on, the IP core includes a JTAG to Avalon-MM Master bridge connecting internally to status and reconfiguration registers. This allows to run the Ethernet Link Inspector using the System Console.

AN/LT Options

Enable AN/LT

Boolean

  • True
  • False

False

If this parameter is turned on, the IP core supports auto negotiation as defined in IEEE Standard 802.3-2015 Clause 73 and the 25G Ethernet Consortium Schedule Draft 1-6, and link training as defined in IEEE Standard 802.3-2015 Clauses 92 and 93 and the 25G Ethernet Consortium Schedule Draft 1-6.

If this parameter is turned off, the IP core does not support these features, and the other parameters on this tab are not available.

Status clock rate Integer 100–162 MHz 100 MHz Sets the expected incoming i_reconfig_clk frequency. The input clock frequency must match the frequency you specify for this parameter.

The IP core is configured with this information to ensure the IP core measures the link fail inhibit time accurately (determines the value of the Link Fail Inhibit timer (IEEE 802.3 clause 73.10.2) correctly).

Auto Negotiation

Enable Auto Negotiation

Boolean

  • True
  • False

True

If this parameter is turned on, the IP core includes logic to implement auto negotiation as defined in Clause 73 of IEEE Std 802.3–2015. If this parameter is turned off, the IP core does not include auto negotiation logic and cannot perform auto negotiation.

Link fail inhibit time

Integer

500–510 ms

504 ms

Specifies the time before link status is set to FAIL or OK. A link fails if the time duration specified by this parameter expires before link status is set to OK. For more information, refer to Clause 73 Auto Negotiation for Backplane Ethernet in IEEE Standard 802.3–2015.

The IP core asserts the o_rx_pcs_ready signal to indicate link status is OK.

Enable CR Technology Ability

Boolean

  • True
  • False
True

If this parameter is turned on, the IP core advertises CR capability by default. If this parameter is turned off, but auto negotiation is turned on, the IP core advertises KR capability by default.

Auto Negotiation Master

Option
  • Lane 0
  • Lane 1
  • Lane 2
  • Lane 3

Lane 0

Selects the master channel for auto negotiation.

The IP core does not provide a mechanism to change the master channel dynamically. The value you set in the parameter editor cannot be changed during operation.

For 100G Ethernet rate, all options are available.

Pause ability–C0

Boolean

  • True
  • False

True

If this parameter is turned on, the IP core indicates on the Ethernet link that it supports symmetric pauses as defined in Annex 28B of Section 2 of IEEE Std 802.3–2015.

Pause ability–C1

Boolean

  • True
  • False

True

If this parameter is turned on, the IP core indicates on the Ethernet link that it supports asymmetric pauses as defined in Annex 28B of Section 2 of IEEE Std 802.3–2015.

Link Training

Enable Link Training

Boolean

  • True
  • False

True

If this parameter is turned on, the IP core includes the link training module, which configures the remote link partner TX PMD for the lowest Bit Error Rate (BER). LT is defined in Clause 92 of IEEE Std 802.3–2015.

Number of frames to send at end of training

Integer
  • 127
  • 255
127

Specifies the number of additional training frames the local link partner delivers after training is complete to ensure that the link partner can correctly detect the local receiver state.

Enable Clause 72 PRBS11 generation

Boolean

  • True
  • False
False If turned on, the IP core includes logic to generate the legacy Clause 72 PRBS pattern, in addition to the 25G Link Training patterns specified in Clause 92 of the IEEE Std 802.3–2015. If turned off, the IP core generates only the 25G Link Training patterns specified in Clause 92 of the IEEE Std 802.3–2015.

Link Training: PMA Parameters

VMAXRULE

Integer 0–31 30

Specifies the maximum VOD. The default value, 30, represents 1200 mV. This default value is the maximum value the device should drive.

VMINRULE

Integer 0–31 6

Specifies the minimum VOD. The default value, 6, represents 165 mV. This default value is the minimum value the device should drive.

VODMINRULE

Integer 0–31 14

Specifies the minimum VOD for the first tap.

The default value, 14, represents 440 mV.

VPOSTRULE

Integer 0–25 25

Specifies the maximum value that the internal algorithm for pre-emphasis will ever test in determining the optimum post-tap setting.

VPRERULE

Integer 0–16 16

Specifies the maximum value that the internal algorithm for pre-emphasis will ever test in determining the optimum pre-tap setting.

PREMAINVAL

Integer 0–31 30

Specifies the Preset VOD value. This value is set by the Preset command of the link training protocol, defined in Clause 72.6.10.2.3.1 of IEEE Std 802.3–2015.

PREPOSTVAL

Integer 0–25 0

Specifies the preset Post-tap value.

PREPREVAL

Integer 0–16 0

Specifies the preset Pre-tap value.

INITMAINVAL

Integer 0–31 25

Specifies the initial VOD value. This value is set by the Initialize command of the link training protocol, defined in Clause 72.6.10.2.3.2 of IEEE Std 802.3–2015.

INITPOSTVAL

Integer 0–25 13

Specifies the initial Post-tap value.

INITPREVAL

Integer 0–16 3

Specifies the initial Pre-tap value.
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