|tx_serial[3:0]||Output||TX transceiver data. Each tx_serial bit becomes two physical pins that form a differential pair.|
|rx_serial[3:0]||Input||RX transceiver data. Each rx_serial bit becomes two physical pins that form a differential pair.|
The input clock clk_ref is the reference clock for the transceiver RX CDR PLL and the RS-FEC PLLs.This clock must have a frequency of 644.53125 or 322.265625 MHz with a ±100 ppm accuracy per the IEEE 802.3ba-2010 Ethernet Standard.
In addition, clk_ref must meet the jitter specification of the IEEE 802.3ba-2010 Ethernet Standard.
The PLL and clock generation logic use this reference clock to derive the transceiver and PCS clocks. The input clock should be a high quality signal on the appropriate dedicated clock pin. Refer to the relevant device datasheet for transceiver reference clock phase noise specifications.
|tx_serial_clk[1:0]||Input||High speed serial clocks driven by the two ATX PLLs. The frequency of these clocks is 12.890625 GHz.
You must drive these clocks from the two ATX PLLs that you configure separately from the Low Latency 100G Ethernet Intel FPGA core.
|tx_pll_locked[1:0]||Input||Lock signals from the two ATX PLLs. Each bit indicates the corresponding ATX PLL is locked.|
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