Low Latency 100G Ethernet Intel® FPGA IP Core User Guide: For Intel® Stratix® 10 Devices

ID 683100
Date 2/16/2022
Document Table of Contents

6.3. Transceivers

The transceivers implement four CAUI-4 physical lanes at 25.78125 MHz and require two separately instantiated advanced transmit (ATX) PLLs to generate the high speed serial clocks. On Intel® Stratix® 10 devices, only the ATX PLL supports the required data rate.
Table 14.   Transceiver Signals




tx_serial[3:0] Output TX transceiver data. Each tx_serial bit becomes two physical pins that form a differential pair.
rx_serial[3:0] Input RX transceiver data. Each rx_serial bit becomes two physical pins that form a differential pair.
clk_ref Input

The input clock clk_ref is the reference clock for the transceiver RX CDR PLL and the RS-FEC PLLs.

This clock must have a frequency of 644.53125 or 322.265625 MHz with a ±100 ppm accuracy per the IEEE 802.3ba-2010 Ethernet Standard.

In addition, clk_ref must meet the jitter specification of the IEEE 802.3ba-2010 Ethernet Standard.

The PLL and clock generation logic use this reference clock to derive the transceiver and PCS clocks. The input clock should be a high quality signal on the appropriate dedicated clock pin. Refer to the relevant device datasheet for transceiver reference clock phase noise specifications.

tx_serial_clk[1:0] Input High speed serial clocks driven by the two ATX PLLs. The frequency of these clocks is 12.890625 GHz.

You must drive these clocks from the two ATX PLLs that you configure separately from the Low Latency 100G Ethernet Intel FPGA core.

tx_pll_locked[1:0] Input Lock signals from the two ATX PLLs. Each bit indicates the corresponding ATX PLL is locked.

Did you find the information on this page useful?

Characters remaining:

Feedback Message