Low Latency 100G Ethernet Intel® FPGA IP Core User Guide: For Intel® Stratix® 10 Devices

ID 683100
Date 2/16/2022
Public
Document Table of Contents

7.8.12. Auto Negotiation Status Register 3

This register provides the lower bits of the AN RX Next page received from the link partner.

Offset: 0xC9

Access: RO

Auto Negotiation Status Register 3 Fields

Bit Name Description Access Reset
15:0 lp_next_page_low Link Partner Next Page (lower bits)

[15]: Link partner next page bit

[14]: Link partner ACK

[13]: Link partner MP bit

[12]: Link partner ACK2 bit

[11]: Link partner Toggle bit

[10:0]: Link partner Message/Unformatted bits

RO 0x0

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