Low Latency 100G Ethernet Intel® FPGA IP Core User Guide: For Intel® Stratix® 10 Devices

ID 683100
Date 2/16/2022
Public
Document Table of Contents

7.8.1. AN/LT Sequencer Config

Provides the following config bits:
  • Reset AN/LT Sequencer
  • Disable AN Timer
  • Disable Link Fail Timer
  • Force Sequencer Mode
  • Link Training failure response
  • Link Fail if HiBER on/off
  • Skip LT on AN timeout when HiBER not used on/off

Offset: 0xB0

Access: RW

AN/LT Sequencer Config Fields

Bit Name Description Access Reset
14 skip_lt_on_an_timeout Skip Link Training on Auto Negotiation Timeout

1: If AN times out skip LT before attempting data mode, and use the previous LT settings

0: Use the normal AN/LT sequence, even if link_fail_if_hiber=0

  • This option is provided to speed up re-lock times when the link is known not to be resetting due to problems with link integrity
RW 0x0
13 link_fail_if_hiber Link Fail if HiBER

1: Trigger a link failure if a HiBER condition is detected in the PCS during data mode (default)

0: Ignore HiBER

RW 0x1
12 lt_failure_response Link Training Failure Response

1: Upon LT failure, PHY will go to data mode

0: Upon LT failure, PHY will restart AN, or if AN is disabled, skip AN and restart LT

  • This CSR defaults to 0 in hardware (synthesis)
  • We recommend setting this to 1 for simulation to avoid the need to model line conditions
RW 0x0
7:4 seq_force_mode Force the sequencer into a specific protocol

4'b0000: No force

4'b0011: 100GBASE-R4

All other settings are reserved

  • Forces the AN/LT Sequencer into a specific protocol, ignoring the AN result
  • AN/LT will still be cycled if enabled; configure AN and LT using their respective CFG registers
RW 0x0
2 disable_lf_timer Disable Link Fail Inhibit Timer

1: Disable the link fail inhibit timer

0: If PCS link fails, then AN will restart

  • The most common reason to disable the link fail inhibit timer is to characterize the link's behavior with link training
  • Turning off the link fail inhibit timer prevents link training from cycling, allowing each failure to be examined individually
RW 0x0
1 disable_an_timer Disable Auto Negotiation Timer

1: AN will wait for valid partner without timing out (default)

0: If AN fails, the Sequencer will try a different protocol

RW 0x1
0 reset_seq Reset AN/LT Sequencer

1: Reset only the AN/LT Sequencer. May initiate a PCS reconfiguration and/or AN/LT reset

0: Normal operation

RW 0x0

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