Low Latency 100G Ethernet Intel® FPGA IP Core User Guide: For Intel® Stratix® 10 Devices

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ID 683100
Date 2/16/2022
Public
Document Table of Contents

11. Document Revision History for the Low Latency 100G Ethernet Intel FPGA IP Core User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2022.02.16 21.1 19.2.0 Added "Low Latency 100G Ethernet KR/CR Variant: IP-ETH-100GEUKRCR" to Ordering Codes to enable KR/CR (AN/LT)
2021.05.21 21.1 19.2.0 Removed support for the Intel Agilex™ device family.
2020.09.28 20.3 Made the following changes:
  • Revised title from Low Latency 100G Ethernet Intel® Stratix® 10 FPGA IP Core User Guide to Low Latency 100G Ethernet Intel FPGA IP Core User Guide: For Intel® Stratix® 10 and Intel® Agilex™ Devices. The user guide supports Intel® Stratix® 10 and Intel® Agilex™ devices.
  • Added support for Intel® Agilex™ devices.
  • Updated Performance and Resource Utilization section:
    • Updated resource utilization for Intel® Stratix® 10 devices in the IP Core FPGA Resource Utilization for Intel® Stratix® 10 Devices table.
    • Added resource utilization for Intel® Agilex™ devices in the IP Core FPGA Resource Utilization for Intel® Agilex™ Devices table.
  • Updated the Low Latency 100G Ethernet Intel FPGA IP Signals and Interfaces figure.
  • Removed flow control signals from the TX/RX MAC Interface to User Logic sections. Created a new Flow Control Interface topic to include pause_isert_tx0/tx1 and pause_insert_rx signals.
  • Corrected the width of the reconfiguration address from reconfig_address[13:0] to reconfig_address[12:0].
  • Revised figure displaying the traffic on the TX Avalon® -ST client interface in the TX MAC Interface to User Logic section.
  • Added new sections:
    • Auto Adaptation
    • Ethernet Toolkit
2020.04.13 20.1 19.2.0 Made the following changes:
  • Updated information on PLL configuration in the Adding the Transceiver PLLs section. The TX transceiver PLLs are instantiated with two Intel® Stratix® 10 ATX PLL IP cores, one as the main ATX PLL and another as a clock buffer.
  • Added PMA registers word offset in the Low Latency 100G Ethernet Intel FPGA IP Core Register Map Overview table.
2020.03.16 19.4 19.1.1
  • Updated Intel® Stratix® 10 device family support status from Advance to Final in the Low Latency 100G Ethernet Intel FPGA IP Core Device Family Support table.
  • Removed the updated PLL configuration information in the Adding the Transceiver PLLs section.
  • Updated information on multichannel configuration in the Disabling Background Calibration section.
2019.12.16 19.4 19.1.1
  • Updated information on PLL configuration in the Adding the Transceiver PLLs section.
  • Added pause_insert_tx0 and pause_insert_tx1 signals in the Signals of the Avalon® streaming interfaceTX Client Interface table.
  • Added pause_receive_rx signal in the Signals of the Avalon® streaming interfaceRX Client Interface table.
  • Added a new topic: Disabling Background Calibration.
  • Updated description of RX PFC Enable in the RX Flow Control Registers table.
  • Removed KHZ_REF from PHY Registers table.
  • Updated description of EIO_RX_SOFT_PURGE_S[12] in the PHY Registers table.
2019.08.02 19.2 19.1.1
  • Replaced Altera Debug Master Endpoint (ADME) with Native PHY Debug Master Endpoint (NPDME).
  • Added ATX PLL reference clock clarification in the Adding the Transceiver PLLs section.
  • Updated EIO_RX_SOFT_PURGE_S signal in the Registers section.
  • Added IP versioning description in the Released Information section.
2018.09.24 18.1
  • Updated the IP core block diagram.
  • Added feature support for Auto-negotiation (AN) and Link training (LT).
  • Added new parameters for AN/LT Options.
  • Added a new section: Auto-Negotiation and Link Training.
  • Added registers under a new section: Auto-Negotiation and Link Training Registers.
  • Added register for dynamic control of RS-FEC block in the Table: PHY Registers.
2018.07.18 18.0
  • Added flow control, TX error insertion, and RX control frame indication features in supported features list.
  • Updated release information for the IP core.
  • Added 322.265625 MHz clock option to the PHY reference frequency parameter.
  • Added Enable MAC Flow Control, Number of queues in priority flow control, and Enable link fault generation parameters in the IP core parameter table.
  • Added PCS compliance table Functional Description section.
  • Added pause_insert_tx0, pause_insert_tx1, and pause_receive_rx signals in the Low Latency 100G Ethernet Intel FPGA Signals and Interfaces diagram.
  • Updated PHY_CONFIG and RX_FEC_STATUS registers' default value.
  • Added ERR_INJ, LINK_FAULT, Pause/PFC Flow Control registers in the Registers section.
  • Added Inter-Packet Gap Adjustment topic.
  • Updated the clk_status and reconfig_clk frequency to 100 - 162 MHz.
2017.11.06 17.1 Initial public release.

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