Low Latency 100G Ethernet Intel® FPGA IP Core User Guide: For Intel® Stratix® 10 Devices

ID 683100
Date 2/16/2022
Public
Document Table of Contents

7.8.9. Auto Negotiation Config Register 6

Provides the upper bits of the User Controlled Auto Negotiation Next Page

Offset: 0xC6

Access: RW

Auto Negotiation Config Register 6 Fields

Bit Name Description Access Reset
31:0 user_next_page_high User Controlled AN Next page (upper bits)

[31:0]: Unformatted Code Field (or [47:16] when MP bit is low)

RW 0x0

Did you find the information on this page useful?

Characters remaining:

Feedback Message