Low Latency 100G Ethernet Intel® FPGA IP Core User Guide: For Intel® Stratix® 10 Devices

ID 683100
Date 2/16/2022
Public
Document Table of Contents

7.8.14. Auto Negotiation Status Register 5

This register provides the following status information:
  • Link Partner Technology Ability Field
  • Link Partner Remote Fault
  • Link Partner PAUSE Ability

Offset: 0xCB

Access: RO

Auto Negotiation Status Register 5 Fields

Bit Name Description Access Reset
30:28 an_lp_adv_pause Link Partner PAUSE Ability bits

[0]: PAUSE as defined in Annex 28B

[1]: ASM_DIR as defined in Annex 28B

[2]: Reserved

RO 0x0
27 an_lp_adv_remote_fault Link Partner Remote Fault

Remote fault bit from Link Partner

RO 0x0
22:0 an_lp_adv_tech_a Link Partner Technology Ability Field

[6]: 100GBASE-KP4

[7]: 100GBASE-KR4

[8]: 100GBASE-CR4

[22:11]: Reserved

RO 0x0

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