Low Latency 100G Ethernet Intel® FPGA IP Core User Guide: For Intel® Stratix® 10 Devices

Download
ID 683100
Date 2/16/2022
Public
Document Table of Contents

1.3.1. Simulation Environment

Intel performs the following tests on the Low Latency 100G Ethernet Intel FPGA IP core in the simulation environment using internal and third-party standard bus functional models (BFM):

  • Constrained random tests that cover randomized frame size and contents
  • Randomized error injection tests that inject Frame Check Sequence (FCS) field errors, runt packets, and corrupt control characters, and then check for the proper response from the IP core
  • Assertion based tests to confirm proper behavior of the IP core with respect to the specification
  • Extensive coverage of our runtime configuration space and proper behavior in all possible modes of operation

Did you find the information on this page useful?

Characters remaining:

Feedback Message