Low Latency 100G Ethernet Intel® FPGA IP Core User Guide: For Intel® Stratix® 10 Devices

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ID 683100
Date 2/16/2022
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Document Table of Contents
Document Table of Contents x
1. Low Latency 100G Ethernet Intel FPGA IP Overview 2. Getting Started 3. IP Core Parameters 4. Functional Description 5. Reset 6. Interfaces and Signal Descriptions 7. Registers 8. Debugging the Link 9. Ethernet Toolkit Overview 10. Low Latency 100G Ethernet Intel FPGA IP Core User Guide Archives 11. Document Revision History for the Low Latency 100G Ethernet Intel FPGA IP Core User Guide
1. Low Latency 100G Ethernet Intel FPGA IP Overview x
1.1. Low Latency 100G Ethernet Intel FPGA IP Core Supported Features 1.2. IP Core Device Family and Speed Grade Support 1.3. IP Core Verification 1.4. Performance and Resource Utilization 1.5. Release Information
1.2. IP Core Device Family and Speed Grade Support x
1.2.1. Low Latency 100G Ethernet Intel FPGA IP Core Device Family Support 1.2.2. Low Latency 100G Ethernet Intel FPGA IP Core Device Speed Grade Support
1.3. IP Core Verification x
1.3.1. Simulation Environment 1.3.2. Compilation Checking 1.3.3. Hardware Testing
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying the IP Core Parameters and Options 2.3. Simulating the IP Core 2.4. Generated File Structure 2.5. Integrating Your IP Core in Your Design 2.6. IP Core Testbenches 2.7. Compiling the Full Design and Programming the FPGA
2.5. Integrating Your IP Core in Your Design x
2.5.1. Pin Assignments 2.5.2. Adding the Transceiver PLLs 2.5.3. Placement Settings for the Low Latency 100G Ethernet Intel FPGA IP Core
4. Functional Description x
4.1. High Level System Overview 4.2. Low Latency 100G Ethernet Intel FPGA IP Core TX Datapath 4.3. Low Latency 100G Ethernet Intel FPGA IP Core RX Datapath 4.4. Flow Control 4.5. User Interface to Ethernet Transmission 4.6. Auto Negotiation and Link Training 4.7. Auto Adaptation
4.2. Low Latency 100G Ethernet Intel FPGA IP Core TX Datapath x
4.2.1. Preamble, Start, and SFD Insertion 4.2.2. Length/Type Field Processing 4.2.3. Frame Padding 4.2.4. Frame Check Sequence (CRC-32) Insertion 4.2.5. Inter-Packet Gap Adjustment 4.2.6. Error Insertion Test and Debug Feature 4.2.7. TX PCS 4.2.8. TX RSFEC
4.3. Low Latency 100G Ethernet Intel FPGA IP Core RX Datapath x
4.3.1. Low Latency 100G Ethernet Intel FPGA IP Core Preamble Processing 4.3.2. IP Core Strict SFD Checking 4.3.3. Low Latency 100G Ethernet Intel FPGA IP Core FCS (CRC-32) Removal 4.3.4. Low Latency 100G Ethernet Intel FPGA IP Core CRC Checking 4.3.5. Low Latency 100G Ethernet Intel FPGA IP Core Malformed Packet Handling 4.3.6. RX CRC Forwarding 4.3.7. Inter-Packet Gap 4.3.8. RX PCS 4.3.9. RX RSFEC
4.4. Flow Control x
4.4.1. TX Pause/PFC Flow Control Transmission 4.4.2. XON/XOFF Pause Frames
4.5. User Interface to Ethernet Transmission x
4.5.1. Order of Transmission 4.5.2. Bit Order For TX and RX Datapaths
6. Interfaces and Signal Descriptions x
6.1. TX MAC Interface to User Logic 6.2. RX MAC Interface to User Logic 6.3. Transceivers 6.4. Transceiver Reconfiguration Signals 6.5. Avalon-MM Management Interface 6.6. Miscellaneous Status and Debug Signals 6.7. Reset Signals 6.8. Clocks 6.9. Flow Control Interface
6.4. Transceiver Reconfiguration Signals x
6.4.1. Disabling Background Calibration
7. Registers x
7.1. PHY Registers 7.2. TX MAC Registers 7.3. RX MAC Registers 7.4. Pause/PFC Flow Control Registers 7.5. Statistics Registers 7.6. TX Reed-Solomon FEC Registers 7.7. RX Reed-Solomon FEC Registers 7.8. Auto-Negotiation and Link Training Registers
7.5. Statistics Registers x
7.5.1. TX Statistics Registers 7.5.2. RX Statistics Registers
7.8. Auto-Negotiation and Link Training Registers x
7.8.1. AN/LT Sequencer Config 7.8.2. AN/LT Sequencer Status 7.8.3. Auto Negotiation Config Register 1 7.8.4. Auto Negotiation Config Register 2 7.8.5. Auto Negotiation Status Register 7.8.6. Auto Negotiation Config Register 3 7.8.7. Auto Negotiation Config Register 4 7.8.8. Auto Negotiation Config Register 5 7.8.9. Auto Negotiation Config Register 6 7.8.10. Auto Negotiation Status Register 1 7.8.11. Auto Negotiation Status Register 2 7.8.12. Auto Negotiation Status Register 3 7.8.13. Auto Negotiation Status Register 4 7.8.14. Auto Negotiation Status Register 5 7.8.15. Link Training Config Register 1 7.8.16. Link Training Config Register 2 7.8.17. Link Training Status Register 1 7.8.18. Link Training Config Register for Lane 0 7.8.19. Link Training Frame Contents for Lane 0 7.8.20. Local Transceiver TX EQ 1 Settings for Lane 0 7.8.21. Local Transceiver TX EQ 2 Settings for Lane 0 7.8.22. Local Link Training Parameters 7.8.23. Link Training Config Register for Lane 1 7.8.24. Link Training Frame Contents for Lane 1 7.8.25. Local Transceiver TX EQ 1 Settings for Lane 1 7.8.26. Local Transceiver TX EQ 2 Settings for Lane 1 7.8.27. Link Training Config Register for Lane 2 7.8.28. Link Training Frame Contents for Lane 2 7.8.29. Local Transceiver TX EQ 1 Settings for Lane 2 7.8.30. Local Transceiver TX EQ 2 Settings for Lane 2 7.8.31. Link Training Config Register for Lane 3 7.8.32. Link Training Frame Contents for Lane 3 7.8.33. Local Transceiver TX EQ 1 Settings for Lane 3 7.8.34. Local Transceiver TX EQ 2 Settings for Lane 3
9. Ethernet Toolkit Overview x
9.1. Features
1. Low Latency 100G Ethernet Intel FPGA IP Overview
2. Getting Started
3. IP Core Parameters
4. Functional Description
5. Reset
6. Interfaces and Signal Descriptions
7. Registers
8. Debugging the Link
9. Ethernet Toolkit Overview
10. Low Latency 100G Ethernet Intel FPGA IP Core User Guide Archives
11. Document Revision History for the Low Latency 100G Ethernet Intel FPGA IP Core User Guide

7.1. PHY Registers

Table 23.  PHY RegistersThe global hard reset csr_rst_n resets all of these registers. The TX reset tx_rst_n and RX reset rx_rst_n signals do not reset these registers.
Addr Name Description Reset Access
0x300 REVID IP core PHY module revision ID 0x0809 2017 RO
0x301 SCRATCH Scratch register available for testing 0x0000 0000 RW
0x302 PHY_NAME_0 First characters of IP core variation identifier string, "100". 0x0031 3030 RO
0x303 PHY_NAME_1 Next characters of IP core variation identifier string, "GE". 0x0000 4745 RO
0x304 PHY_NAME_2 Final characters of IP core variation identifier string, "pcs". 0x0070 6373 RO
0x310 PHY_CONFIG PHY configuration registers. The following bit fields are defined:
  • Bit[0]: : eio_sys_rst. Full system reset (except registers). Set this bit to initiate the internal reset sequence.
  • Bit[1]: soft_txp_rst. TX soft reset.
  • Bit[2]: soft_rxp_rst. RX soft reset.
  • Bit[3]: Reserved.
  • Bit[4]: set_ref_lock. Directs the RX CDR PLL to lock to the reference clock.
  • Bit[5]: set_data_lock. Directs the RX CDR PLL to lock to data.
  • Bits[31:6]: Reserved.
The reset bits are not self-clearing. To force a reset, you can set and reset a reset bit in back-to-back register write operations. 		26'hX_2'b0_1'bX_3'b0

(X= don't care)

RW
0x312 WORD_LOCK Each of the 20 lower order bits, when asserted, indicates that the corresponding virtual channel has identified 66 bit block boundaries in the serial data stream.

If Enable RS-FEC is turned on, the value is always zero.

0xXXX0 0000

(X= don't care)

RO
0x313 EIO_SLOOP Serial PMA loopback. Setting a bit puts the corresponding transceiver in serial loopback mode. In serial loopback mode, the TX lane loops back to the RX lane on an internal loopback path. 0xXXXX XXX0 RW
0x314 EIO_FLAG_SEL Supports indirect addressing of individual FIFO flags in the 10G PCS Native PHY IP core. Program this register with the encoding for a specific FIFO flag. The flag values (one per transceiver) are then accessible in the EIO_FLAGS register.

The value in the EIO_FLAG_SEL register directs the IP core to make available the following FIFO flag:

  • 3'b000: TX FIFO full
  • 3'b001: TX FIFO empty
  • 3'b010: TX FIFO partially full
  • 3'b011: TX FIFO partially empty
  • 3'b100: RX FIFO full
  • 3'b101: RX FIFO empty
  • 3'b110: RX FIFO partially full
  • 3'b111: RX FIFO partially empty
29'bX_3'b000 RW
0x315 EIO_FLAGS PCS indirect data. To read a FIFO flag, set the value in the EIO_FLAG_SEL register to indicate the flag you want to read. After you specify the flag in the EIO_FLAG_SEL register, each bit [n] in the EIO_FLAGS register has the value of that FIFO flag for the transceiver channel for lane [n]. 0xXXXX XXX0 RO
0x321 EIO_FREQ_LOCK Each of the lower order four bits, when asserted, indicates that the corresponding lane RX clock data recovery (CDR) phase-locked loop (PLL) is locked. 0xXXXX XXX0 RO
0x322 PHY_CLK The following encodings are defined:
  • Bit[0]: If set to 1, indicates the TX transceivers have completed reset.
  • Bit [1]: If set to 1, indicates the TX core clock is stable. And if the Enable RS-FEC is turned on, the FEC TX PLL has acquired frequency lock.
  • Bit[2]: If set to 1, indicates the RX core clock is stable. And if the Enable RS-FEC is turned on, the FEC RX PLL has acquired frequency lock.
29'bX_3'b000 RO
0x323 FRM_ERR

Each of the 20 lower order bits, when asserted, indicates that the corresponding virtual lane has a frame error. You can read this register to determine if the IP core sustains a low number of frame errors, below the threshold to lose word lock. These bits are sticky, unless the virtual lane loses word lock. Write 1'b1 to the SCLR_FRM_ERR register to clear.

If a virtual lane loses word lock, it clears the corresponding register bit.

Each bit in this register has a valid value only if the corresponding bit in the WORD_LOCK register at offset 0x312 has the value of 1.

If Enable RS-FEC is turned on, the value is always zero.

0xXXX0 0000 RO
0x324 SCLR_FRM_ERR Synchronous clear for FRM_ERR register. Write 1'b1 to this register to clear the FRM_ERR register and bit [1] of the LANE_DESKEWED register. A single bit clears all sticky framing errors.

This bit does not auto clear. Write a 1'b0 to continue logging frame errors.

0x0000 0000 RW
0x325 EIO_RX_SOFT_PURGE_S Set bit [0] to clear the RX FIFO for all four physical lanes.
  • Bit[11]: If set to 1, disables the bitslip request from PCS to PMA.
  • Bit[12]: If set to 1, holds auto adaptation module in Idle state. If set to 0, releases auto adaptation module from the Idle state.
0x0000 0000 RW
0x326 RX_PCS_FULLY_ALIGNED_S Indicates the RX PCS is fully aligned and ready to accept traffic.
  • Bit[0]: RX PCS fully aligned status.
  • Bit[1]: RX PCS HI BER status.

If Enable RS-FEC is turned on, the value is always zero.

30'bX_2'b00

RO
0x327 ERR_INJ When set to 1, injects an error in the corresponding lane. The register is rising-edge triggered. Write a 0 to clear. 0xXXXX XXX0 RW
0x328 AM_LOCK When bit [0] is asserted, indicates that the IP core has identified virtual lane alignment markers in the data stream of all 20 virtual lanes, and has ordered the virtual lanes.

If Enable RS-FEC is turned on, the value is always zero.

0xXXXX XXX0 RO
0x329 LANE_DESKEWED The following encodings are defined:
  • Bit [0]: Indicates all lanes are deskewed.
  • Bit [1]: When asserted indicates a change in lanes deskewed status. To clear this sticky bit, write 1'b1 to the corresponding bit of the SCLR_FRM_ERR register. This is a latched signal.

If Enable RS-FEC is turned on, the value is always zero.

30'bX_2'b00

 RO
0x330 PCS_VLANE0 PCS virtual lane mapping. Identifies the five virtual lanes detected on physical lane 0. Virtual lanes are encoded with the five-bit binary virtual lane number. One virtual lane index is encoded in register bits [4:0], another in register bits [9:5], another in register bits [14:10], another in register bits [19:15], and another in register bits [24:20].

For example, if the value of the register is 25'b00001_00101_00011_00000_01000, virtual lanes 0, 1, 3, 5, and 8 map to physical lane 0.

The value 0x1F in any of these fields indicates no virtual lane is recorded yet. Before the IP core asserts rx_pcs_ready, transitional values can appear in the register fields. Therefore, you should read the register three to four times to ensure you read the correct virtual lane indicators.

If Enable RS-FEC is turned on, the value remains at the reset value.

0x01FF FFFF RO
0x331 PCS_VLANE1 PCS virtual lane mapping for physical lane 1.

The value 0x1F in any of these fields indicates no virtual lane is recorded yet. Before the IP core asserts rx_pcs_ready, transitional values can appear in the register fields. Therefore, you should read the register three to four times to ensure you read the correct virtual lane indicators.

If Enable RS-FEC is turned on, the value remains at the reset value.

0x01FF FFFF RO
0x332 PCS_VLANE2 PCS virtual lane mapping for physical lane 2.

The value 0x1F in any of these fields indicates no virtual lane is recorded yet. Before the IP core asserts rx_pcs_ready, transitional values can appear in the register fields. Therefore, you should read the register three to four times to ensure you read the correct virtual lane indicators.

If Enable RS-FEC is turned on, the value remains at the reset value.

0x01FF FFFF RO
0x333 PCS_VLANE3 PCS virtual lane mapping for physical lane 3.

The value 0x1F in any of these fields indicates no virtual lane is recorded yet. Before the IP core asserts rx_pcs_ready, transitional values can appear in the register fields. Therefore, you should read the register three to four times to ensure you read the correct virtual lane indicators.

If Enable RS-FEC is turned on, the value remains at the reset value.

0x01FF FFFF RO
0x341 KHZ_RX RX clock (clk_rxmac) frequency in KHz, assuming the clk_status clock has the frequency of 100 MHz. The RX clock frequency is the value in this register times the frequency of the clk_status clock, divided by 100. 0x0000 0000 RO
0x342 KHZ_TX TX clock (clk_txmac) frequency in KHz, assuming the clk_status clock has the frequency of 100 MHz. The TX clock frequency is the value in this register times the frequency of the clk_status clock, divided by 100. 0x0000 0000 RO
0x343 KHZ_TX_RS FEC TX clock (clk_tx_rs) frequency in KHz, assuming the clk_status clock has the frequency of 100 MHz. The TX FEC clock frequency is the value in this register times the frequency of the clk_status clock, divided by 100.

This register is available only if Enable RS-FEC is turned on.

0x0000 0000 RO
0x344 KHZ_RX_RS FEC RX clock (clk_rx_rs) frequency in KHz, assuming the clk_status clock has the frequency of 100 MHz. The RX FEC clock frequency is the value in this register times the frequency of the clk_status clock, divided by 100.

This register is available only if Enable RS-FEC is turned on.

0x0000 0000 RO
0x350 ENABLE_RSFEC

Allows you to dynamically control the RS-FEC block which is part of the data path. This register is available only if the Enable RS-FEC is turned on.

When the RS-FEC block is enabled, writing 1 enables the RS-FEC data path and writing 0 disables the RS-FEC data path.
Note: In a configuration where the RS-FEC + KR feature is enabled, this register has no effect because the data path always includes the RS-FEC by default.
0x0000 0001 RW
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