Low Latency 100G Ethernet Intel® FPGA IP Core User Guide: For Intel® Stratix® 10 Devices

ID 683100
Date 2/16/2022
Public
Document Table of Contents

4.3.8. RX PCS

The soft RX PCS interfaces to the hard PCS and PMA blocks configured in 66:64 25G PCS Basic Generic Mode, with bitslip enabled. The hard PCS drives two, 66-bit output streams containing four virtual lanes to the soft RX PCS. The soft RX PCS implements word lock, lane reordering, descrambling, and MII decoding.
Figure 10. High Level Block Diagram of the Soft RX PCS

PCS Compliance

The Low Latency 100G Ethernet Intel FPGA IP RX PCS individual lock stages are designed to offer maximum compliance while reducing design resources. Hence, the design is not fully compliant to IEEE 802.3 Clause 82 specification. The non-compliance lock and unlock processes are listed in the following table.

Table 11.  RX PCS Non-Compliance ListLock and unlock processes which are not listed in this table are compliance to the IEEE 802.3 specification.
Process Description
Virtual lane re-ordering lock

IEEE specification: The virtual lanes re-ordering is initiated when alignment lock gets acquired.

Low Latency 100G Ethernet Intel FPGA IP core: The virtual lane reordering is initiated by block lock.

PCS lane deskew lock
IEEE specification: Deskew lock is acquired when the following conditions are met:
  • Alignment lock is acquired
  • Virtual lanes re-ordering completed
  • Lanes deskew completed

Low Latency 100G Ethernet Intel FPGA IP core: The PCS lane deskew lock is initiated after virtual lanes reordering is complete.

PCS alignment lock
IEEE specification: Alignment lock is acquired when the following conditions are met:
  • Block lock is acquired
  • All virtual lanes alignment markers are received at proper alignment interval of 214 words per virtual lanes for two consecutive cycles

Low Latency 100G Ethernet Intel FPGA IP core: The alignment lock happens after PCS lane deskew lock is completed and interval frequency checking of individual markers for each virtual lane is complete.

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