Low Latency 100G Ethernet Intel® FPGA IP Core User Guide: For Intel® Stratix® 10 Devices

ID 683100
Date 2/16/2022
Document Table of Contents

7.8.31. Link Training Config Register for Lane 3

Provides CSRs for the following link training features:
  • LT PRBS Pattern Select for lane 3
  • LT PRBS Seed for lane 3

Offset: 0xE8

Access: RW

Link Training Config Register for Lane 3 Fields

Bit Name Description Access Reset
26:16 lt_prbs_seed_ln3 Link Training PRBS Seed for Lane 3

Sets the initial seed for PRBS. Default value is 11'h7b6

RW 0x7B6
2:0 lt_prbs_pattern_select_ln3 Link Training PRBS Pattern Select for Lane 3

0: Use Clause 92 Polynomial 0

1: Use Clause 92 Polynomial 1

2: Use Clause 92 Polynomial 2

3: Use Clause 92 Polynomial 3

4: Use Clause 72 Polynomial (if CL72 PRBS parameter is enabled)

All other settings reserved

  • Default value for lane 3 is 3
RW 0x3

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