Low Latency 100G Ethernet Intel® FPGA IP Core User Guide: For Intel® Stratix® 10 Devices

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ID 683100
Date 2/16/2022
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7.7. RX Reed-Solomon FEC Registers

Table 31.  RX Reed-Solomon FEC Registers
Addr Name Bit Description Reset Access
0xD00 REVID [31:0] RSFEC RX module revision ID 0x0809 2017 RO
0xD01 RX_RSFEC_SCRATCH [31:0] Scratch register available for testing. 32'b0 RW
0xD02 RX_RSFEC_NAME0 [31:0] Final 4 characters of IP core variation identifier string, "100gRSFECoRX". 0x436F 5258 RO
0xD03 RX_RSFEC_NAME1 [31:0] Middle 4 characters of IP core variation identifier string, "100gRSFECoRX". 0x5253 4645 RO
0xD04 RX_RSFEC_NAME2 [31:0] Initial 4 characters of IP core variation identifier string, "100gRSFECoRX". 0x3130 3067 RO
0xD05 BYPASS_RESTART [4] Restart state machines. When 1'b1, specifies the IP core restarts the FEC synchronization and alignment state machines. Bit self-clears after alignment marker synchronization is restarted. (Refer to Figure 91-8 and Figure 91-9 in IEEE Standard 802.3bj-2014). 0x0000 0000 RW
[3:1] Reserved.
[0] Bypass RS-FEC decoder. When 1'b1, specifies the IP core bypasses the RS-FEC decoder. When 1'b0, enables RS-FEC error correction.
0xD06 RX_FEC_STATUS [15:8] fec_lane: Two bits per lane hold the FEC lane number when the corresponding amps_lock bit (in register bits [3:0]) has the value of 1. The following encodings are defined:
  • Bits[15:14]: fec_lane for lane 3
  • Bits[13:12]: fec_lane for lane 2
  • Bits[11:10]: fec_lane for lane 1
  • Bits[9:8]: fec_lane for lane 0
0x0000 FF00 RO
[7:5] Reserved.
[4] fec_align_status: Alignment marker lock status. When 1'b1, indicates all lanes are synchronized and aligned. When 1'b0, indicates the deskew process is not yet complete. (Refer to Figure 91-9 in IEEE Standard 802.3bj-2014).
[3:0] amps_lock: Each bit indicates that the receiver has detected the location of the alignment marker payload sequence for the corresponding FEC lane. (Refer to Figure 91-8 in IEEE Standard 802.3bj-2014).
0xD07 CORRECTED_CW [31:0] 32-bit counter that contains the number of corrected FEC codewords processed. The value resets to zero upon read and holds at max count.

This register gets updated based on the error correction logic even when BYPASS_RESTART bit [0] is 1.

0x0000 0000 RC
0xD08 UNCORRECTED_CW [31:0] 32-bit counter that contains the number of uncorrected FEC codewords processed. The value resets to zero upon read and holds at max count.

This register gets updated based on the error correction logic even when BYPASS_RESTART bit [0] is 1.

0x0000 0000 RC

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