Low Latency 100G Ethernet Intel® FPGA IP Core User Guide: For Intel® Stratix® 10 Devices

ID 683100
Date 2/16/2022
Public

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7.8.33. Local Transceiver TX EQ 1 Settings for Lane 3

Provides the following Local TX EQ 1 Settings for Lane 3
  • Local TX EQ VOD Setting for Lane 3
  • Local TX EQ Post-Tap Setting for Lane 3
  • Local TX EQ Pre-Tap Setting for Lane 3

Offset: 0xEA

Access: RO

Local Transceiver TX EQ 1 Settings for Lane 3 Fields

Bit Name Description Access Reset
20:16 lt_pretap_setting_ln3 Local TX EQ Pre-tap Setting for Lane 3

This register returns the most recent Pre-tap setting that was written to the local transceiver.

RO 0x0
13:8 lt_posttap_setting_ln3 Local TX EQ Post-tap Setting for Lane 3

This register returns the most recent Post-tap setting that was written to the local transceiver

RO 0x0
4:0 lt_vod_setting_ln3 Local TX EQ VOD Setting for Lane 3

This register returns the most recent VOD setting that was written to the local transceiver

RO 0x0