Visible to Intel only — GUID: mfo1495493381218
Ixiasoft
Visible to Intel only — GUID: mfo1495493381218
Ixiasoft
1.4. Performance and Resource Utilization
Resource utilization changes depending on the parameter settings you specify in the Low Latency 100G Ethernet Intel FPGA IP parameter editor. For example, if you turn on RS-FEC in the Low Latency 100G Ethernet Intel FPGA parameter editor, the IP core requires additional resources to implement the additional functionality.
IP Core Variation | A | B | C | D | E |
---|---|---|---|---|---|
Parameter | |||||
Enable RS-FEC | — | — | On | — | On |
Enable TX CRC insertion | — | On | On | On | On |
Enable preamble passthrough | — | — | — | On | On |
Enable RX/TX statistics counters | — | On | On | On | On |
LL 100GbE Variation |
ALMs |
Dedicated Logic Registers |
Memory M20K |
---|---|---|---|
A | 24,877 | 58,120 | 40 |
B | 29,557 | 67,190 | 40 |
C | 57,472 | 135,615 | 100 |
D | 29,380 | 66,876 | 40 |
E | 57,053 | 134,649 | 100 |
Did you find the information on this page useful?
Feedback Message
Characters remaining: