Low Latency 100G Ethernet Intel® FPGA IP Core User Guide: For Intel® Stratix® 10 Devices

ID 683100
Date 2/16/2022
Document Table of Contents

1.4. Performance and Resource Utilization

Resource utilization changes depending on the parameter settings you specify in the Low Latency 100G Ethernet Intel FPGA IP parameter editor. For example, if you turn on RS-FEC in the Low Latency 100G Ethernet Intel FPGA parameter editor, the IP core requires additional resources to implement the additional functionality.

Table 4.  IP Core Variation Encoding for Resource Utilization Tables"On" indicates the parameter is turned on. The symbol "—" indicates the parameter is turned off or not available.
IP Core Variation A B C D E
Enable RS-FEC On On
Enable TX CRC insertion On On On On
Enable preamble passthrough On On
Enable RX/TX statistics counters On On On On
Table 5.  IP Core FPGA Resource Utilization for Intel® Stratix® 10 DevicesLists the resources and expected performance for selected variations of the IP core, from one compilation of each IP core variation. Your results may vary depending on your overall design.

These results were obtained using the Intel® Quartus® Prime Pro Edition v20.3 software.

Note: Resource utilization numbers for variations with RS-FEC enabled, reflect preliminary results for the RS-FEC feature. The resource utilization for this block might vary by up to 5% in the final implementation of this feature.
  • The numbers of ALMs and logic registers are rounded up to the nearest 100.
  • The numbers of ALMs, before rounding, are the ALMs needed numbers from the Intel® Quartus® Prime Fitter Report.

LL 100GbE Variation


Dedicated Logic Registers



A 24,877 58,120 40
B 29,557 67,190 40
C 57,472 135,615 100
D 29,380 66,876 40
E 57,053 134,649 100