Low Latency 100G Ethernet Intel® FPGA IP Core User Guide: For Intel® Stratix® 10 Devices

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ID 683100
Date 2/16/2022
Public
Document Table of Contents

7.8.10. Auto Negotiation Status Register 1

This register provides the lower bits of the AN RX Base page received from the link partner

Offset: 0xC7

Access: RO

Auto Negotiation Status Register 1 Fields

Bit Name Description Access Reset
15:0 lp_base_page_low Link Partner Base Page (lower bits)

[15]: Link partner next page bit

[14]: Link partner ACK

[13]: Link partner RF bit

[12:10]: Link partner PAUSE bits

[9:5]: Link partner Echoed Nonce bits

[4:0]: Link partner Selector bits

RO 0x0

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