Low Latency 100G Ethernet Intel® FPGA IP Core User Guide: For Intel® Stratix® 10 Devices

ID 683100
Date 2/16/2022
Public
Document Table of Contents

7. Registers

This section provides information about the memory-mapped registers. You access these registers using the IP core Avalon-MM control and status interface. The registers use 32-bit addresses; they are not byte addressable.

Write operations to a read-only register field have no effect. Read operations that address a Reserved register return an unspecified result. Write operations to Reserved registers have no effect. Accesses to registers that do not exist in your IP core variation, or to register bits that are not defined in your IP core variation, have an unspecified result. You should consider these registers and register bits Reserved. Although you can only access registers in 32-bit read and write operations, you should not attempt to write or ascribe meaning to values in undefined register bits.

Table 22.   Low Latency 100G Ethernet Intel FPGA IP Core Register Map OverviewLists the main ranges of the memory mapped registers for the Low Latency 100G Ethernet Intel FPGA IP core. Addresses are word addresses.

Word Offset

Register Category

0x00B0-0x00EB Auto Negotiation and Link Training registers
0x0300–0x03FF PHY registers
0x0400–0x04FF TX MAC registers
0x0500–0x05FF RX MAC registers
0x0800–0x08FF TX statistics counters
0x0900–0x09FF RX statistics counters
0x0C00–0x0CFF TX RS-FEC registers
0x0D00–0x0DFF RX RS-FEC registers
0x4000-0x7FFF PMA registers 1
1 Each PHY channel has its PMA registers set. PMA registers sets are offset from each other by 0x800 channel offset, starting at the 0x4000 word offset.

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