Low Latency 100G Ethernet Intel® FPGA IP Core User Guide: For Intel® Stratix® 10 Devices

ID 683100
Date 2/16/2022
Document Table of Contents

2.6. IP Core Testbenches

Intel provides a compilation-only design example and a testbench with certain variations of the Low Latency 100G Ethernet Intel FPGA IP core.

To generate the testbench, in the IP parameter editor, you must first set the parameter values for the IP core variation you intend to generate in your end product. If you do not set the parameter values for your DUT to match the parameter values in your end product, the testbench you generate does not exercise the IP core variation you intend. If your IP core variation does not meet the criteria for a testbench, the parameter editor provides warnings and the design example generation process creates a testbench that does not function correctly.

The testbench demonstrates a basic test of the IP core. It is not intended to be a substitute for a full verification environment.