Low Latency 100G Ethernet Intel® FPGA IP Core User Guide: For Intel® Stratix® 10 Devices

ID 683100
Date 2/16/2022
Public
Document Table of Contents

7.8.7. Auto Negotiation Config Register 4

Provides the upper bits of the User Controlled Auto Negotiation Base Page

Offset: 0xC4

Access: RW

Auto Negotiation Config Register 4 Fields

Bit Name Description Access Reset
31:0 user_base_page_high User Controlled AN Base page (upper bits)

[29:5]: Technology Ability bits

[4:0]: TX Nonce bits

RW 0x0

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