Low Latency 100G Ethernet Intel® FPGA IP Core User Guide: For Intel® Stratix® 10 Devices

ID 683100
Date 2/16/2022
Document Table of Contents

6.5. Avalon-MM Management Interface

You access control and status registers using an Avalon® -MM management interface. The interface responds regardless of the link status. It also responds when the IP core is in a reset state driven by any reset signal or soft reset other than the csr_rst_n signal. Asserting the csr_rst_n signal resets all control and status registers except the statistics counters; while this reset is in process, the Avalon-MM management interface does not respond.

This interface cannot handle multiple pending read transfers. Despite the presence of the status_readdata_valid signal, this Avalon-MM interface is non-pipelined with variable latency.

Table 16.   Avalon-MM Management Interface




clk_status Input The clock that drives the control and status registers. The frequency of this clock is 100-162 MHz.
status_addr[15:0] Input

Drives the Avalon® -MM register address.

status_read Input

When asserted, specifies a read request.

status_write Input When asserted, specifies a write request.
status_readdata[31:0] Output Drives read data. Valid when status_readdata_valid is asserted.
status_readdata_valid Output When asserted, indicates that status_read_data[31:0] is valid.
status_writedata[31:0] Input Drives the write data.
status_waitrequest Output Indicates that the control and status interface is not ready to complete the transaction. status_waitrequest is only used for read transactions.