Low Latency 100G Ethernet Intel® FPGA IP Core User Guide: For Intel® Stratix® 10 Devices

ID 683100
Date 2/16/2022
Document Table of Contents

5. Reset

Control and Status registers control three parallel soft resets. These soft resets are not self-clearing. Software clears them by writing to the appropriate register. In addition, the IP core has three hard reset signals.

Asserting the external hard reset csr_rst_n returns all Control and Status registers to their original values, including the statistics counters. An additional dedicated reset signal resets the transceiver reconfiguration interface.

Figure 16. Conceptual Overview of General IP Core Reset LogicThe three hard resets are top-level ports. The three soft resets are internal signals which are outputs of the PHY_CONFIG register. Software writes the appropriate bit of the PHY_CONFIG to assert a soft reset.

The general reset signals reset the following functions:

  • soft_tx_rst, tx_rst_n: Resets the IP core in the TX direction. Resets the TX PCS, TX MAC, and digital portion of the transceiver. This reset leads to deassertion of the tx_lanes_stable output signal.
  • soft_rx_rst, rx_rst_n: Resets the IP core in the RX direction. Resets the RX PCS and RX MAC. This reset leads to deassertion of the rx_pcs_ready output signal.
  • sys_rst, csr_rst_n: Resets the IP core. Resets the TX and RX MACs, PCS, and transceivers.
    Note: csr_rst_n resets the Control and Status registers, including the statistics counters. sys_rst does not reset any Control and Status registers.
    This reset leads to deassertion of the tx_lanes_stable and rx_pcs_ready output signals.

In addition, the synchronous reconfig_reset signal resets the IP core transceiver reconfiguration interface, an Avalon-MM interface. Associated clock is the reconfig_clk, which clocks the transceiver reconfiguration interface.

System Considerations

You should perform a system reset before beginning IP core operation, preferably by asserting the csr_rst_n signal.

If you assert the transmit reset when the downstream receiver is already aligned, the receiver loses alignment. Before the downstream receiver loses lock, it might receive some malformed frames.

If you assert the receive reset while the upstream transmitter is sending packets, the packets in transit are corrupted.

If the ATX PLL loses lock, the IP core forces a transmit side reset. After the ATX PLL acquires lock, the IP core deasserts the transmit reset.

If the IP core suffers loss of signal on the serial links, it asserts the receive reset.