Low Latency 100G Ethernet Intel® FPGA IP Core User Guide: For Intel® Stratix® 10 Devices

Download
ID 683100
Date 2/16/2022
Public
Document Table of Contents

6.7. Reset Signals

The IP core has three external hard reset inputs. These resets are asynchronous and are internally synchronized. Assert resets for ten clk_status cycles or until you observe the effect of their specific reset. Asserting the external hard reset csr_rst_n returns control and status registers to their original values. rx_pcs_ready and tx_lanes_stable are asserted when the core has exited reset successfully.
Table 18.   Reset Signals

Signal

Direction

Description

tx_rst_n Input Active low hard reset signal. Resets the TX interface, including the TX PCS and TX MAC. This reset leads to the deassertion of the tx_lanes_stable output signal.
rx_rst_n Input

Active low hard reset signal. Resets the RX interface, including the RX PCS and RX MAC. This reset leads to the deassertion of the rx_pcs_ready output signal.

csr_rst_n Input

Active low hard global reset. Resets the full IP core. Resets the TX MAC, RX MAC, TX PCS, RX PCS,transceivers, and control and status registers. This reset leads to the deassertion of the tx_lanes_stable and rx_pcs_ready output signals.

Did you find the information on this page useful?

Characters remaining:

Feedback Message