Low Latency 100G Ethernet Intel® FPGA IP Core User Guide: For Intel® Stratix® 10 Devices

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ID 683100
Date 2/16/2022
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Document Table of Contents
Document Table of Contents x
1. Low Latency 100G Ethernet Intel FPGA IP Overview 2. Getting Started 3. IP Core Parameters 4. Functional Description 5. Reset 6. Interfaces and Signal Descriptions 7. Registers 8. Debugging the Link 9. Ethernet Toolkit Overview 10. Low Latency 100G Ethernet Intel FPGA IP Core User Guide Archives 11. Document Revision History for the Low Latency 100G Ethernet Intel FPGA IP Core User Guide
1. Low Latency 100G Ethernet Intel FPGA IP Overview x
1.1. Low Latency 100G Ethernet Intel FPGA IP Core Supported Features 1.2. IP Core Device Family and Speed Grade Support 1.3. IP Core Verification 1.4. Performance and Resource Utilization 1.5. Release Information
1.2. IP Core Device Family and Speed Grade Support x
1.2.1. Low Latency 100G Ethernet Intel FPGA IP Core Device Family Support 1.2.2. Low Latency 100G Ethernet Intel FPGA IP Core Device Speed Grade Support
1.3. IP Core Verification x
1.3.1. Simulation Environment 1.3.2. Compilation Checking 1.3.3. Hardware Testing
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying the IP Core Parameters and Options 2.3. Simulating the IP Core 2.4. Generated File Structure 2.5. Integrating Your IP Core in Your Design 2.6. IP Core Testbenches 2.7. Compiling the Full Design and Programming the FPGA
2.5. Integrating Your IP Core in Your Design x
2.5.1. Pin Assignments 2.5.2. Adding the Transceiver PLLs 2.5.3. Placement Settings for the Low Latency 100G Ethernet Intel FPGA IP Core
4. Functional Description x
4.1. High Level System Overview 4.2. Low Latency 100G Ethernet Intel FPGA IP Core TX Datapath 4.3. Low Latency 100G Ethernet Intel FPGA IP Core RX Datapath 4.4. Flow Control 4.5. User Interface to Ethernet Transmission 4.6. Auto Negotiation and Link Training 4.7. Auto Adaptation
4.2. Low Latency 100G Ethernet Intel FPGA IP Core TX Datapath x
4.2.1. Preamble, Start, and SFD Insertion 4.2.2. Length/Type Field Processing 4.2.3. Frame Padding 4.2.4. Frame Check Sequence (CRC-32) Insertion 4.2.5. Inter-Packet Gap Adjustment 4.2.6. Error Insertion Test and Debug Feature 4.2.7. TX PCS 4.2.8. TX RSFEC
4.3. Low Latency 100G Ethernet Intel FPGA IP Core RX Datapath x
4.3.1. Low Latency 100G Ethernet Intel FPGA IP Core Preamble Processing 4.3.2. IP Core Strict SFD Checking 4.3.3. Low Latency 100G Ethernet Intel FPGA IP Core FCS (CRC-32) Removal 4.3.4. Low Latency 100G Ethernet Intel FPGA IP Core CRC Checking 4.3.5. Low Latency 100G Ethernet Intel FPGA IP Core Malformed Packet Handling 4.3.6. RX CRC Forwarding 4.3.7. Inter-Packet Gap 4.3.8. RX PCS 4.3.9. RX RSFEC
4.4. Flow Control x
4.4.1. TX Pause/PFC Flow Control Transmission 4.4.2. XON/XOFF Pause Frames
4.5. User Interface to Ethernet Transmission x
4.5.1. Order of Transmission 4.5.2. Bit Order For TX and RX Datapaths
6. Interfaces and Signal Descriptions x
6.1. TX MAC Interface to User Logic 6.2. RX MAC Interface to User Logic 6.3. Transceivers 6.4. Transceiver Reconfiguration Signals 6.5. Avalon-MM Management Interface 6.6. Miscellaneous Status and Debug Signals 6.7. Reset Signals 6.8. Clocks 6.9. Flow Control Interface
6.4. Transceiver Reconfiguration Signals x
6.4.1. Disabling Background Calibration
7. Registers x
7.1. PHY Registers 7.2. TX MAC Registers 7.3. RX MAC Registers 7.4. Pause/PFC Flow Control Registers 7.5. Statistics Registers 7.6. TX Reed-Solomon FEC Registers 7.7. RX Reed-Solomon FEC Registers 7.8. Auto-Negotiation and Link Training Registers
7.5. Statistics Registers x
7.5.1. TX Statistics Registers 7.5.2. RX Statistics Registers
7.8. Auto-Negotiation and Link Training Registers x
7.8.1. AN/LT Sequencer Config 7.8.2. AN/LT Sequencer Status 7.8.3. Auto Negotiation Config Register 1 7.8.4. Auto Negotiation Config Register 2 7.8.5. Auto Negotiation Status Register 7.8.6. Auto Negotiation Config Register 3 7.8.7. Auto Negotiation Config Register 4 7.8.8. Auto Negotiation Config Register 5 7.8.9. Auto Negotiation Config Register 6 7.8.10. Auto Negotiation Status Register 1 7.8.11. Auto Negotiation Status Register 2 7.8.12. Auto Negotiation Status Register 3 7.8.13. Auto Negotiation Status Register 4 7.8.14. Auto Negotiation Status Register 5 7.8.15. Link Training Config Register 1 7.8.16. Link Training Config Register 2 Link Training Config Register 2 Fields 7.8.17. Link Training Status Register 1 7.8.18. Link Training Config Register for Lane 0 7.8.19. Link Training Frame Contents for Lane 0 7.8.20. Local Transceiver TX EQ 1 Settings for Lane 0 7.8.21. Local Transceiver TX EQ 2 Settings for Lane 0 7.8.22. Local Link Training Parameters 7.8.23. Link Training Config Register for Lane 1 7.8.24. Link Training Frame Contents for Lane 1 7.8.25. Local Transceiver TX EQ 1 Settings for Lane 1 7.8.26. Local Transceiver TX EQ 2 Settings for Lane 1 7.8.27. Link Training Config Register for Lane 2 7.8.28. Link Training Frame Contents for Lane 2 7.8.29. Local Transceiver TX EQ 1 Settings for Lane 2 7.8.30. Local Transceiver TX EQ 2 Settings for Lane 2 7.8.31. Link Training Config Register for Lane 3 7.8.32. Link Training Frame Contents for Lane 3 7.8.33. Local Transceiver TX EQ 1 Settings for Lane 3 7.8.34. Local Transceiver TX EQ 2 Settings for Lane 3
9. Ethernet Toolkit Overview x
9.1. Features
1. Low Latency 100G Ethernet Intel FPGA IP Overview
2. Getting Started
3. IP Core Parameters
4. Functional Description
5. Reset
6. Interfaces and Signal Descriptions
7. Registers
8. Debugging the Link
9. Ethernet Toolkit Overview
10. Low Latency 100G Ethernet Intel FPGA IP Core User Guide Archives
11. Document Revision History for the Low Latency 100G Ethernet Intel FPGA IP Core User Guide

7.8.16. Link Training Config Register 2

Provides CSRs for the following link training features:
  • Restart Link Training on Lane 0
  • Restart Link Training on Lane 1
  • Restart Link Training on Lane 2
  • Restart Link Training on Lane 3
  • Updated Link Partner TX EQ Override Settings ready to be sent for Lane 0
  • Updated Link Partner TX EQ Override Settings ready to be sent for Lane 1
  • Updated Link Partner TX EQ Override Settings ready to be sent for Lane 2
  • Updated Link Partner TX EQ Override Settings ready to be sent for Lane 3
  • Updated Local TX EQ Override Settings ready to be sent for Lane 0
  • Updated Local TX EQ Override Settings ready to be sent for Lane 1
  • Updated Local TX EQ Override Settings ready to be sent for Lane 2
  • Updated Local TX EQ Override Settings ready to be sent for Lane 3

Offset: 0xD1

Access: RW

Link Training Config Register 2 Fields

Bit Name Description Access Reset
11 updated_local_coef_ln3 Updated Local TX EQ Override Settings ready to be set for Lane 3

1: Trigger LT logic to set new Local TX EQ Override settings for Lane 3

0: Normal operation

Valid only when ovride_local_coef_enable=1.

Takes values from corresponding TX EQ Override CSR.

RW 0x0
10 updated_local_coef_ln2 Updated Local TX EQ Override Settings ready to be set for Lane 2

1: Trigger LT logic to set new Local TX EQ Override settings for Lane 2

0: Normal operation

Valid only when ovride_local_coef_enable=1.

Takes values from corresponding TX EQ Override CSR

RW 0x0
9 updated_local_coef_ln1 Updated Local TX EQ Override Settings ready to be set for Lane 1

1: Trigger LT logic to set new Local TX EQ Override settings for Lane 1

0: Normal operation

Valid only when ovride_local_coef_enable=1.

Takes values from corresponding TX EQ Override CSR.

RW 0x0
8 updated_local_coef_ln0 Updated Local TX EQ Override Settings ready to be set for Lane 0

1: Trigger LT logic to set new Local TX EQ Override settings for Lane 0

0: Normal operation

Valid only when ovride_local_coef_enable=1

Takes values from corresponding TX EQ Override CSR

RW 0x0
7 updated_lp_coef_ln3 Updated Link Partner TX EQ Override Settings ready to be sent for Lane 3

1: Trigger LT logic to transmit new TX EQ Override settings for Link Partner Lane 3

0: Normal operation

Valid only when ovride_lp_coef_enable=1

Takes values from corresponding TX EQ Override CSR.

RW 0x0
6 updated_lp_coef_ln2 Updated Link Partner TX EQ Override Settings ready to be sent for Lane 2

1: Trigger LT logic to transmit new TX EQ Override settings for Link Partner Lane 2

0: Normal operation

Valid only when ovride_lp_coef_enable=1.

Takes values from corresponding TX EQ Override CSR.

RW 0x0
5 updated_lp_coef_ln1 Updated Link Partner TX EQ Override Settings ready to be sent for Lane 1

1: Trigger LT logic to transmit new TX EQ Override settings for Link Partner Lane 1

0: Normal operation

Valid only when ovride_lp_coef_enable=1

Takes values from corresponding TX EQ Override CSR.

RW 0x0
4 updated_lp_coef_ln0 Updated Link Partner TX EQ Override Settings ready to be sent for Lane 0

1: Trigger LT logic to transmit new TX EQ Override settings for Link Partner Lane 0

0: Normal operation

Valid only when ovride_lp_coef_enable=1.

Takes values from corresponding TX EQ Override CSR.

RW 0x0
3 restart_link_training_ln3 Restart Link Training on lane 3

1: Restart Clause 93 start-up protocol

0: Normal operation

  • Corresponds to state variable mr_restart_training as defined in IEEE 802.3 CL 72.6.10.3.1
RW 0x0
2 restart_link_training_ln2 Restart Link Training on lane 2

1: Restart Clause 93 start-up protocol

0: Normal operation

  • Corresponds to state variable mr_restart_training as defined in IEEE 802.3 CL 72.6.10.3.1
RW 0x0
1 restart_link_training_ln1 Restart Link Training on lane 1

1: Restart Clause 93 start-up protocol

0: Normal operation

  • Corresponds to state variable mr_restart_training as defined in IEEE 802.3 CL 72.6.10.3.1
RW 0x0
0 restart_link_training_ln0 Restart Link Training on lane 0

1: Restart Clause 93 start-up protocol

0: Normal operation

  • Corresponds to state variable mr_restart_training as defined in IEEE 802.3 CL 72.6.10.3.1
RW 0x0
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