Low Latency 100G Ethernet Intel® FPGA IP Core User Guide: For Intel® Stratix® 10 Devices

ID 683100
Date 2/16/2022
Document Table of Contents

7.2. TX MAC Registers

Table 24.  TX MAC Registers
Addr Name Description Reset Access
0x400 TXMAC_REVID TX MAC revision ID. 0x0809 2017 RO
0x401 TXMAC_SCRATCH Scratch register available for testing. 0x0000 0000 RW
0x402 TXMAC_NAME_0 First 4 characters of IP core variation identifier string, "100g". 0x3130 3067


0x403 TXMAC_NAME_1

Next 4 characters of IP core variation identifier string, "MACT".

0x4D41 4354


0x404 TXMAC_NAME_2 Final 4 characters of IP core variation identifier string, "xCSR". 0x7843 5352



Link Fault Configuration Register. The following bits are defined:

  • Force Remote Fault bit[3]: When link fault generation is enabled, stops data transmission and forces transmission of a remote fault.
  • Disable Remote Fault bit[2]: When both link fault reporting and unidirectional transport are enabled, the core transmits data and does not transmit remote faults (RF). This bit takes effect when the value of this register is 28'hX4'b0111.
  • Unidir Enable bit[1]: When asserted, the core includes Clause 66 support for the remote link fault reporting on the Ethernet link.
  • Link Fault Reporting Enable bit[0]: The following encodings are defined:
    • 1'b1: The PCS generates the proper fault sequence on Ethernet link, when conditions are met.
    • 1'b0: The PCS does not generate the fault sequence.


0x406 IPG_COL_REM Specifies the number of IDLE columns to be removed in every Alignment Marker period to compensate for alignment marker insertion. You can program this register to a larger value than the default value, for clock compensation.

The default value is 20 (decimal)..

Bits [31:8] of this register are Reserved.

0x407 MAX_TX_SIZE_CONFIG Specifies the maximum TX frame length. Frames that are longer are considered oversized. However, the IP core does transmit them.

If the IP core transmits an Ethernet frame of size greater than the number of bytes specified in this register, and the IP core includes statistics registers, the IP core increments the 64-bit CNTR_TX_OVERSIZE counter.

The minimum value of this register is 64 (decimal).

Bits [31:16] of this register are Reserved.

0xXXXX 2580


0x40A TX_MAC_CONTROL TX MAC Control Register. A single bit is defined:
  • Bit [1] – VLAN detection disabled. This bit is deasserted by default, implying VLAN detection is enabled.
30'hX2'b0X RW