HDMI Intel® FPGA IP User Guide

ID 683798
Date 1/30/2023
Public
Document Table of Contents

9.1.1.14. USER_PACKET_STATUS_CONTROL (0x12)

Table 78.  USER_PACKET_STATUS_CONTROL (0x12)
Name Bit(s) Access Description Reset
Number of slots 31:24 RO Number of available slots to write to. 0x0
Reserved 23:20 - - -
Packet slot 19:16 RW Slot number to write packet data to. 0x0
reserved 15:2 - - -
Packet mode 1 RW When set, the contents of the user packet carousel are automatically cleared after sending. When cleared, all defined user packets continue to be sent every frame. 0x0
Interface busy 0 RO This bit is set to 1'b1 when the user packet interface is busy waiting for the current write to complete. Software should poll this register prior to updating the user packet carousel contents, otherwise data may be lost. 0x0

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