HDMI Intel® FPGA IP User Guide

ID 683798
Date 1/30/2023
Public
Document Table of Contents

6.1. Sink Functional Description

The HDMI sink core provides direct connection to the Transceiver Native PHY through a 20-bit or 40-bit parallel data path. The clock domains for the auxiliary and audio ports, and the internal modules are different for FRL path and non-FRL path.
Figure 48. HDMI Sink Signal Flow Diagram for TMDS (Support FRL = 0) DesignThe figure below shows the flow of the HDMI sink signals. The figure shows the various clocking domains used within the core.

The sink core provides three (TMDS mode) or four (FRL mode) 20-bit or 40-bit data input paths corresponding to the color channels. The sink core clocks the three 20-bit or 40-bit channels from the transceiver outputs using the respective transceiver clock outputs.

  • Blue channel: 0
  • Green channel: 1
  • Red channel: 2
  • Clock channel: 3
Figure 49. HDMI Sink Signal Flow Diagram for Support FRL = 1 and Active Video Protocol = None Design

For Support FRL = 1 design, in TMDS mode, a DCFIFO clocks the HDMI data stream from the scrambler, TMDS/TERC4 decoder in the transceiver recovered clock domain to vid_clk domain. All the blocks in the FRL path and video data operate in vid_clk domain.

When operating TMDS mode, the sink core accepts three 20-bit data input paths corresponding to each color channel. The sink core clocks the three 20-bit channels from the transceiver outputs using respective transceiver clock outputs.

  • Blue channel: Data channel 0
  • Green channel: Data channel 1
  • Red channel: Data channel 2
Note: Data channel 3 is unused in TMDS mode. Data channels 0–3 are always 40-bit wide, but only 20 bits from the least significant bits are used in TMDS mode.

When operating in FRL mode, the sink core accepts four 40-bit data input paths corresponding to each FRL channel. The sink core clocks the four 40-bit channels from the transceiver outputs using respective transceiver clock outputs.

  • FRL channel 0: Data channel 0
  • FRL channel 1: Data channel 1
  • FRL channel 2: Data channel 2
  • FRL channel 3: Data channel 3

The sink core provides N*48 bit video data per channel for each color channel, where N is number of pixels per clock.

Figure 50. HDMI Sink Signal Flow Diagram for Support FRL =1 and Active Video Protocol = AXIS-VVP Full

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