HDMI Intel® FPGA IP User Guide

ID 683798
Date 1/30/2023
Public
Document Table of Contents

9.2.2.22. VIDEO_MODE_VERTICAL_SYNC_POLARITY (0x6C)

Table 121.  VIDEO_MODE_VERTICAL_SYNC_POLARITY (0x6C)
Name Bit(s) Access Description Reset
Reserved 31:1 - - -
Video mode vertical sync polarity 0 RW
  • Set to 1 for positive vertical sync polarity.
  • Set to 0 for negative vertical sync polarity.
0x0

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