6.6. Sink Deep Color Implementation When Support FRL = 1
vid_clk frequency = 225 MHz
In deep color mode, the video data (30 bpp, 36 bpp, or 48 bpp) in the vid_clk domain has higher throughput than the data in the ls_clk domain. The HDMI RX core uses the vid_valid signal to indicate the validity of the video data at a specific clock.
If your user logic cannot process the video data at a faster rate, you can use a DCFIFO to clock cross the video data from vid_clk to the actual pixel clock as shown in the diagram below. The wren signal of the DCFIFO IP connects to the vid_valid signal from the HDMI RX core. The rden signal is always asserted.
When operating in 10 bits per color, the vid_ready signal is high for 4 out of 5 clock cycles. For every 5 clock cycles, the HDMI RX core receives 4 valid video data with 10 bits per color.
The timing diagrams and description below assume that the video data at the vid_clk domain is running at the actual deep color data rate. If the video data at the vid_clk domain is running faster than the actual deep color data rate, the vid_valid signal would toggle more.