HDMI Intel® FPGA IP User Guide

ID 683798
Date 7/29/2022
Public
Document Table of Contents

4.3.1.14.3. Source Reconfiguration Controller

The Nios II CPU acts as the multirate reconfiguration controller for the HDMI source.

The CPU relies on the periodic rate detection from the Multirate Reconfig Controller (RX) to determine if TX requires reconfiguration. The Avalon-MM slave translator provides the interface between the Nios II processor Avalon-MM master interface and the Avalon-MM slave interfaces of the externally instantiated HDMI source's PLL Reconfig Intel FPGA IP and Transceiver Native PHY (TX).

Figure 12. Nios II Software FlowThe reconfiguration sequence flow for TX is the same as RX, except that the PLL and transceiver reconfiguration, and the reset sequence is performed sequentially. The figure illustrates the Nios II software flow that involves the controls for CVO, I2C master and HDMI source.

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