- 4.1. HDMI Hardware Design Examples for Intel Arria 10, Intel Cyclone 10 GX, Intel Stratix 10, and Intel® Agilex™ F-tile Devices
5.1.23. TX AXI4-Stream Auxiliary Bridge
The AXI4-stream auxiliary interface is a 32-bit wide bus which carries HDMI sideband data such as infoframes or audio packets. It can be used for passthrough purposes when forwarding video from receiver to a transmitter or when used in conjunction with a DMA engine, as a method of saving HDMI packet data to memory with the minimum of CPU overhead.
The packet header is transmitted first, followed by subpacket 0, subpacket 1, subpacket 2 and subpacket 3. Subpacket 0 contains packet bytes 0 to 6 (PB0-PB6), subpacket 1 contains packet byte 7 to 13 (PB7-PB13), subpacket 2 contains packet byte 14 to 20 (PB14-PB20) and subpacket 4 contains packet byte 21 to 27 (PB21-PB27). Refer to HDMI Specification 1.4b Section 220.127.116.11 Data Island Packet Construction for more details on the subpacket. Since each subpacket contains 64 bits, each subpacket is carried by two AXI4-stream auxiliary data of 32-bit wide.
An example transfer sequence for a single complete data packet is shown in the following figure. Transfers conform to the AXI4-stream standard.
The transfer request is initiated by axi4s_aux_in_tvalid going high. The final beat of the transfer is indicated by axi4s_aux_in_tlast going high. All transfers must be exactly nine beats long. The axi4s_aux_in_data needs to be hold when axi4s_aux_in_tready is low.
TX AXI4-stream auxiliary bridge contains a SCFIFO to store the auxiliary data when there is backpressure from the downstream blocks. The default depth of SCFIFO is 16 words.
Did you find the information on this page useful?