HDMI Intel® FPGA IP User Guide

ID 683798
Date 7/29/2022
Public
Document Table of Contents

9.2.2.14. VIDEO_MODE_F0_VERTICAL_FRONT_PORCH (0x5E)

Table 113.  VIDEO_MODE_F0_VERTICAL_FRONT_PORCH (0x5E)
Name Bit(s) Access Description Reset
Reserved 31:16 - - -
F0 vertical front porch 15:0 RW Specifies the length of the field 0 vertical front porch (interlaced video only) in lines. 0x0

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