HDMI Intel® FPGA IP User Guide

ID 683798
Date 7/29/2022
Public
Document Table of Contents

6.1.24. RX Auxiliary Packet Filter

The packet filter block is a register programmable hardware filter which allows the host to select which types of packets are outputted on the AXI4-stream auxiliary bus. It filters the auxiliary packet based on the packet type register AUX_PACKET_FILTER configured by the host processor. Refer to packet type register AUX_PACKET_FILTER for the packet type selection.

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