HDMI Intel® FPGA IP User Guide

ID 683798
Date 7/29/2022
Public
Document Table of Contents

6.5. Sink Deep Color Implementation When Support FRL = 0

When Support FRL = 0, the HDMI RX core requires you to derive vid_clk from ls_clk based on the color depth ratio.

ls_clk frequency = data rate per lane / effective transceiver width

vid_clk frequency = (data rate per lane / effective transceiver width) / color depth ratio

Table 61.  Color Depth Ratio for Bits per Color
Bits per Color Color Depth Ratio
8 1.0
10 1.25
12 1.5
16 2.0
Figure 63. Deep Color Implementation When FRL = 0

When Support FRL = 0, the RX core uses the TMDS clock to drive the IOPLL reference clock. The IOPLL generates three output clocks that drive the CDR reference clock, ls_clk, and vid_clk.

When the HDMI RX core operates in vid_clk and ls_clk with the correct color depth ratio, the vid_valid signal is always high.

Figure 64. 10 Bits per Component (30 Bits per Pixel)When operating in 10 bits per component, the vid_clk frequency to ls_clk frequency ratio is 4:5. For every 5 ls_clk cycles, there should be 4 vid_clk cycles.
Figure 65. 12 Bits per Component (36 Bits per Pixel)When operating in 12 bits per component, the vid_clk frequency to ls_clk frequency ratio is 2:3. For every 3 ls_clk cycles, there should be 2 vid_clk cycles.
Figure 66. 16 Bits per Component (48 Bits per Pixel)When operating in 16 bits per component, the vid_clk frequency to ls_clk frequency ratio is 1:2. For every 1 ls_clk cycle, there should be 2 vid_clk cycles.

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