HDMI Intel® FPGA IP User Guide

ID 683798
Date 1/30/2023
Public
Document Table of Contents

6.1.14. Sink FRL Resampler

FRL resampler consists of the mixed-width DCFIFO to clock the FRL characters from the transceiver recovered clock domain to frl_clk domain.

The mixed-width FIFO buffer demaps the FRL data in effective transceiver width bits to FRL characters per clock*18 bits. For FRL mode, the transceiver width is always 40 bits and number of FRL characters per clock is 8 or 16.

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