5.8. Source Deep Color Implementation When Support FRL = 1
- In TMDS mode:
vid_clk frequency = (data rate per lane / effective transceiver width) / 4
- In FRL mode:
vid_clk frequency = 225 MHz
The vid_ready signal toggles to indicate if the HDMI TX core is ready to take in new video data. In this case, you can use a DCFIFO IP to store the video data when the HDMI TX core is not ready (vid_ready is low). You need to configure the DCFIFO IP to show-ahead mode, with the vid_ready signal connected to the rden signal of the DCFIFO IP.
When vid_ready is low, the DCFIFO IP holds the video data immediately. When vid_ready goes high, the HDMI TX core processes the stored data without losing any valid video data.
The inverted empty signal from the DCFIFO IP sets the vid_valid signal to the HDMI TX core.