HDMI Intel® FPGA IP User Guide

ID 683798
Date 1/30/2023
Public
Document Table of Contents

5.8. Source Deep Color Implementation When Support FRL = 1

When Support FRL = 1, you can drive vid_clk regardless of the color depth ratio.
  • In TMDS mode:

    vid_clk frequency = (data rate per lane / effective transceiver width) / 4

  • In FRL mode:

    vid_clk frequency = 225 MHz

Figure 44. Deep Color Implementation When Support FRL = 1

The vid_ready signal toggles to indicate if the HDMI TX core is ready to take in new video data. In this case, you can use a DCFIFO IP to store the video data when the HDMI TX core is not ready (vid_ready is low). You need to configure the DCFIFO IP to show-ahead mode, with the vid_ready signal connected to the rden signal of the DCFIFO IP.

When vid_ready is low, the DCFIFO IP holds the video data immediately. When vid_ready goes high, the HDMI TX core processes the stored data without losing any valid video data.

The inverted empty signal from the DCFIFO IP sets the vid_valid signal to the HDMI TX core.

Figure 45. 10 Bits per Component (30 Bits per Pixel)When operating in 10 bits per component, the vid_ready signal is high for 4 out of 5 clock cycles. For every 5 clock cycles, the HDMI TX core processes 4 video data with 10 bits per component.
Figure 46. 12 Bits per Component (36 Bits per Pixel)When operating in 12 bits per component, the vid_ready signal is high for 2 out of 3 clock cycles. For every 3 clock cycles, the HDMI TX core processes 2 video data with 12 bits per component.
Figure 47. 16 Bits per Component (48 Bits per Pixel)When operating in 16 bits per component, the vid_ready signal is high for 1 out of 2 clock cycles. For every 2 clock cycles, the HDMI TX core processes 1 video data with 16 bits per component.

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