HDMI Intel® FPGA IP User Guide

ID 683798
Date 1/30/2023
Public
Document Table of Contents

9.4.2.4. F1_ACTIVE_LINE_COUNT (0x54)

Table 153.  F1_ACTIVE_LINE_COUNT (0x54)
Name Bit(s) Access Description Reset
Reserved 31:16 - - -
F1 active line count 15:0 RO The detected line count of the interlaced video field 1 excluding blanking. 0x0

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