6.1.20. Avalon Memory-Mapped Demultiplexer
Avalon memory-mapped demultiplexer demultiplexes a single Avalon slave interface to four Avalon master for HDMI register, Clocked Video to AXI4-stream, EDID RAM and HDCP (for future use) based on the respective address offset. The slave on the Avalon memory-mapped demultiplexer is operating at word addressing.
|EDID RAM||0x0000||16||For HDMI DDC channel for accessing external sink SCDC and EDID and for link training function|
|Clocked Video to AXI4-stream||0x0100||256||Control and status register on Clocked Video to AXI4-stream|
|EDID RAM access||0x0200||1||Indicates host processor is accessing or updating EDID RAM. All other read and write operations to the EDID stop. Upon de-assertion of this signal, RX hotplug signal toggles to trigger the external HDMI source to read the EDID.|
|HDCP register||0x0300||256||Reserved for HDCP registers|
|HDMI register||0x0400||256||Control and status register on HDMI core|
The output data to from the Avalon memory-mapped demultiplexer (AVMM demultiplexer) to HDMI register, Clocked Video to AXI4-stream bridge and HDCP are 32 bits. The write and read operation are channeled through to the respective master according to the address offset. However, EDID RAM has only 8 bits interface due to limitation that the same interface is used by the I2C slave for DDC. Hence, 1 single write operation from the AVMM demultiplexer slave interface of 32-bits data translates into 4 continuous write operation to the EDID RAM with the address increased accordingly on the EDID RAM.
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