HDMI Intel® FPGA IP User Guide

ID 683798
Date 1/30/2023
Public
Document Table of Contents

9.2.2.1. STATUS (0x50)

Table 100.  STATUS (0x50)
Name Bit(s) Access Description Reset
Reserved 31:1 - - -
Status 0 RO When asserted, the AXI2CV is producing data. 0x0

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