HDMI Intel® FPGA IP User Guide

ID 683798
Date 1/30/2023
Public
Document Table of Contents

5.1.15. Source FRL Resampler

FRL resampler consists of the mixed-width DCFIFO to clock the FRL characters from the frl_clk domain to tx_clk domain.

In FRL path, the IP processes video data in FRL characters per clock*18 bits. FRL characters per clock are always 16. The mixed-width FIFO converts the data width into (Number of lanes*Effective transceiver width) bits width. For each link rate, the frl_clk and tx_clk frequency is reconfigured to the specific ratio to keep the throughput of the data the same from frl_clk domain to tx_clk domain.

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