HDMI Intel® FPGA IP User Guide

ID 683798
Date 1/30/2023
Public
Document Table of Contents

9.3.1.4. HOTPLUG (0x04)

Table 127.  HOTPLUG (0x04)
Name Bit Access Description Reset
Reserved 31:1 - - -
Hotplug detect 0 RW Set the value of the hotplug detect signal. 0x1

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